Ajou University repository

Publication Year
2025-01-01
Publisher
Institute of Electrical and Electronics Engineers Inc.
Citation
IEEE Journal of the Electron Devices Society, Vol.13, pp.41-48
Keyword
AC operationCMOS inverterDC operationFD-SOIfrequencylattice temperature profilep/n ratioself-heating effect (SHE)
Mesh Keyword
AC operationCMOS invertersDC operationFrequencyFully depleted silicon-on-insulatorLattice temperature profileLattice-temperatureP/n ratioSelf-heating effectTemperature profiles
All Science Classification Codes (ASJC)
BiotechnologyElectronic, Optical and Magnetic MaterialsElectrical and Electronic Engineering
Abstract
We analyzed the impact of self-heating effect (SHE) on fully depleted-silicon on insulator (FD-SOI) CMOS inverter at the 28 nm technology node, considering both DC and AC operations. Specifically, we focused on investigating the principles behind how SHE influences inverter operating characteristics. To analyze the operating characteristics, we employed 2-D technology computer-aided design (TCAD) mixed mode simulation by Synopsys SentaurusTM. In DC operation, the maximum lattice temperature for n-MOSFET and p-MOSFET are 436 K and 449 K, respectively, resulting in a current degradation of 7.9%. Due to the shifted p/n ratio, the gain also varied, with values of 3.65 V/V for without SHE and 4.21 V/V for with SHE. In AC operation, the maximum temperature varies for each operating frequency: 439 K, 358 K, 324 K, and 319 K, from 10 MHz to 4 GHz. Consequently, the rate of p/n ratio deviation and the rate of voltage change over time vary accordingly. SHE exhibits a faster rate of change, showing a difference of 5.43% at 10 MHz. Analysis of propagation delay through an inverter chain showed a 10% increase at 10 MHz. The results indicate that with SHE, the propagation delay increases, and the slew rate becomes steeper, suggesting improved switching characteristics and gain. However, this unintended consequence highlights the necessity of considering SHE-induced changes in CMOS inverter design to ensure reliable operation.
ISSN
2168-6734
Language
eng
URI
https://dspace.ajou.ac.kr/dev/handle/2018.oak/34686
DOI
https://doi.org/10.1109/jeds.2024.3523286
Fulltext

Type
Article
Funding
This work was supported in part by the National Research Foundation of Korea (NRF) Grant funded by the Korean government (MSIT) under Grant 2022R1A2C1093201 and Grant RS-2024-00406652; in part by the Technology Innovation Program [Development of eGaN HEMT Device Advancement Technology using GaN Standard Modeling Technology (ASM)] funded by the Ministry of Trade, Industry and Energy (MOTIE), South Korea, under Grant 20026440; in part by the Korea Institute for Advancement of Technology (KIAT) Grant funded by the Korea Government (Semiconductor Major Track HR Development Program) under Grant P0022186.
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Lee, Jongmin이종민
Department of Intelligence Semiconductor Engineering
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