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Analysis on Single-Event Transients in Complementary FETs With Heavy Ion Effects
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Publication Year
2025-01-01
Journal
IEEE Transactions on Electron Devices
Publisher
Institute of Electrical and Electronics Engineers Inc.
Citation
IEEE Transactions on Electron Devices
Keyword
Bottom dielectric isolation (BDI)complementary FET (CFET)heavy ionnanosheet FET (NSFET)single-event transient (SET)single-event upset (SEU)
All Science Classification Codes (ASJC)
Electronic, Optical and Magnetic MaterialsElectrical and Electronic Engineering
Abstract
This study presents the first observation of single-event transients (SETs) induced by heavy ions in complementary FETs (CFETs). The influence of radioactive ion particles, such as alpha particles and heavy ions, should be considered in terrestrial environments beyond space or military applications. These particles can generate electron–hole pairs (EHPs) within silicon materials and then unwanted current flows causing soft errors. Nevertheless, the CFET, which is being considered as a candidate for the next-generation CMOS technology, has not been researched yet. Therefore, we evaluated SET characteristics induced by heavy ion particles in the CFET using a commercial TCAD tool (Synopsys Sentaurus TCAD). To understand clearly these radiation effects, gate-all-around (GAA) nanosheet FETs (NSFETs) and CFETs were utilized, and then, transient responses during inverter operations were analyzed. When heavy ions with a track radius smaller than 50 nm were vertically incident at the center of the channel in each structure, it was confirmed that CFET exhibits better immunity to heavy ion effects compared to NSFET, owing to their vertically stacked configuration. Moreover, SET characteristics for CFETs with different stack configurations (i.e., nMOS stacked on pMOS or pMOS stacked on nMOS) were investigated in terms of architecture optimization under radiation. It was found that the radiation effects are dominantly determined by the transistor directly integrated on the substrate. After that, the bottom dielectric isolation (BDI) scheme in the substrate was adopted to suppress EHPs generated by heavy ions, resulting in the reduction of VOUT variations. These results provide guidance for the design of the CFET architecture, considering both device performance and radiation effects.
ISSN
1557-9646
Language
eng
URI
https://aurora.ajou.ac.kr/handle/2018.oak/38383
https://www.scopus.com/inward/record.uri?partnerID=HzOxMe3b&scp=105007435011&origin=inward
DOI
https://doi.org/10.1109/ted.2025.3574277
Journal URL
https://ieeexplore.ieee.org/xpl/mostRecentIssue.jsp?punumber=16
Type
Article
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Kim, Jang Hyun김장현
Department of Electrical and Computer Engineering
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