One-transistor dynamic random-access memory (1T DRAM) offers significant advantages in fabrication process and scalability over the traditional one-transistor one-capacitor (1T-1C) DRAM due to its simplified structure that eliminates the need for capacitors. However, a limitation arises from its single-bit data storage capability, which necessitates scaling down to improve integration density. In this paper, we propose a multi-level cell structure for 1T DRAM to overcome and improve upon these limitations. Through technology computer-aided design (TCAD) simulations, the memory operation of the proposed device is validated, and it is confirmed that using Si0.8Ge0.2 in the data storing region significantly enhances the sensing margin compared to Si. Additionally, the proposed structure is shown to offer advantages over the conventional structure in terms of current variation.
