With the rapid advancement of artificial intelligence (AI), there has been extensive research on AI accelerators to meet the demand for data-intensive analytics. Recently, low-power AI accelerators have been also developed to support battery-operated edge devices and minimize power consumption. However, traditional test architectures are insufficient for effectively testing such low-power AI accelerators. To address this issue, a robust test architecture for low-power AI accelerators has been proposed in this article. The proposed test architecture employs a simple clock-gating technique in systolic array-based low-power AI accelerators and conducts testing through their functional paths. Accordingly, it can achieve 100% test coverage for both stuck-at and transition-delay faults with a minimal number of test patterns. Additionally, the proposed test architecture requires negligible area overhead since only one AND gate is implemented for the entire systolic array in low-power AI accelerators.
This work was supported by the National Research Foundation of Korea(NRF) grant funded by the Korea government(MSIT) (No. 2022R1A2B5B03002504). (Corresponding author: Sungho Kang) Hayoung Lee is with the Department of Intelligence Semiconductor Engineering, Ajou University, Suwon-si, Gyeonggi-do 16499, South Korea (e-mail: hyleee@ajou.ac.kr).
