Queue Time Prediction Methodology in Semiconductor Fab

Abstract

This paper presents a methodology for predicting queue times in semiconductor fabrication, where numerous complex and costly pieces of equipment are utilized. Queue time, occurring between continuous single or multi-processes, is a crucial factor affecting the quality of wafers, which can significantly impact costs. While most semiconductor fabrications use queue time limits as a key dispatching factor, some wafers may still be scrapped or reworked. By predicting queue times, we can reduce unnecessary waste by blocking or re-dispatching wafers. Two approximations are proposed and compared based on accuracy and prediction time: a machine learning model trained using experimental results and a multi-resolution simulation model with varying fidelity levels. The simulation model is validated using the SMAT2022 data set.