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Analysis of Switching Loss Based on Gate Resistance in a SiC MOSFET Inverter
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Publication Year
2023-01-01
Journal
2023 IEEE Conference on Energy Conversion, CENCON 2023
Publisher
Institute of Electrical and Electronics Engineers Inc.
Citation
2023 IEEE Conference on Energy Conversion, CENCON 2023, pp.1-5
Keyword
gate resistanceSiC MOSFETswitching lossswitching time
Mesh Keyword
Drain-source currentsDrain-source voltageGate resistanceHigh frequency HFInverter-basedPaper analysisSiC MOSFETsSwitching lossSwitching timeTotal loss
All Science Classification Codes (ASJC)
Energy Engineering and Power TechnologyRenewable Energy, Sustainability and the EnvironmentAutomotive EngineeringElectrical and Electronic EngineeringMechanical Engineering
Abstract
This paper analyzes the switching loss of a SiC MOSFET inverter based on gate resistance. The design of the gate resistance in the SiC MOSFET is required to prevent malfunctions owing to noise occurring at the gate. The use of gate resistance can reduce noise. However, it causes an increase in switching time - the increase in switching time results in addition to the switching loss of an inverter. When the SiC MOSFET operates at high frequencies, the switching loss constitutes a large portion of the total loss. In this paper, the switching loss is analyzed through the variations in drain-source voltage vDS and drain-source current iDS during the on-off switching. The switching loss based on the gate resistance of the SiC MOSFET inverter is verified using LTSpice simulation.
Language
eng
URI
https://aurora.ajou.ac.kr/handle/2018.oak/36937
https://www.scopus.com/inward/record.uri?partnerID=HzOxMe3b&scp=85182929489&origin=inward
DOI
https://doi.org/10.1109/cencon58932.2023.10369202
Journal URL
http://ieeexplore.ieee.org/xpl/mostRecentIssue.jsp?punumber=10368382
Type
Conference
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Lee, Kyo-Beum이교범
Department of Electrical and Computer Engineering
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