Analysis of Switching Loss Based on Gate Resistance in a SiC MOSFET Inverter

Abstract

This paper analyzes the switching loss of a SiC MOSFET inverter based on gate resistance. The design of the gate resistance in the SiC MOSFET is required to prevent malfunctions owing to noise occurring at the gate. The use of gate resistance can reduce noise. However, it causes an increase in switching time - the increase in switching time results in addition to the switching loss of an inverter. When the SiC MOSFET operates at high frequencies, the switching loss constitutes a large portion of the total loss. In this paper, the switching loss is analyzed through the variations in drain-source voltage vDS and drain-source current iDS during the on-off switching. The switching loss based on the gate resistance of the SiC MOSFET inverter is verified using LTSpice simulation.