Citation Export
DC Field | Value | Language |
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dc.contributor.author | Hamandawana, Prince | - |
dc.contributor.author | Cho, Da Jung | - |
dc.contributor.author | Chung, Tae Sun | - |
dc.date.issued | 2024-11-01 | - |
dc.identifier.issn | 2079-9292 | - |
dc.identifier.uri | https://aurora.ajou.ac.kr/handle/2018.oak/34622 | - |
dc.identifier.uri | https://www.scopus.com/inward/record.uri?partnerID=HzOxMe3b&scp=85210272345&origin=inward | - |
dc.description.abstract | Conventional deduplication systems face critical challenges such as excessive write amplification, high read/write latency, and sub-optimal storage utilization. These limitations often undermine the performance benefits of deduplication by slowing down I/O acknowledgements due to amplified deduplication I/Os, excessive data chunk replication, and strict consistency requirements. To address these issues, we present Speed-Dedup, a novel deduplication framework that employs a deduplicated primary–semi-deduplicated replica object approach. This strategy reduces write amplification by restricting deduplication to the primary object while maintaining a semi-deduplicated replica object used for immediate read/write acknowledgements, thus enhancing I/O latency and storage efficiency. Speed-Dedup also replaces traditional strong consistency models with eventual consistency, allowing for non-blocking read operations and improving overall system throughput. Experimental results demonstrate that Speed-Dedup significantly outperforms traditional methods like GRATE and CAO, showing up to 21% improvement in I/O performance under low deduplication ratios and maintaining 14% or more gains under higher ratios. Additionally, write amplification is substantially reduced and latency improves by over 100% with faster recovery times during system failures. These findings highlight the effectiveness of Speed-Dedup as a scalable and efficient solution. | - |
dc.description.sponsorship | This work was supported by Institute of Information and Communications Technology Planning and Evaluation (IITP) under the Artificial Intelligence Convergence Innovation Human Resources Development (IITP-2024-RS-2023-00255968) grant and the ITRC (Information Technology Research Center) support program (IITP-2021-0-02051) funded by the Korea government (MSIT). Additionally, this work was supported by the BK21 FOUR program of the National Research Foundation of Korea funded by the Ministry of Education (NRF5199991014091). | - |
dc.language.iso | eng | - |
dc.publisher | Multidisciplinary Digital Publishing Institute (MDPI) | - |
dc.title | Speed-Dedup: A New Deduplication Framework for Enhanced Performance and Reduced Overhead in Scale-Out Storage | - |
dc.type | Article | - |
dc.citation.number | 22 | - |
dc.citation.title | Electronics (Switzerland) | - |
dc.citation.volume | 13 | - |
dc.identifier.bibliographicCitation | Electronics (Switzerland), Vol.13 No.22 | - |
dc.identifier.doi | 10.3390/electronics13224393 | - |
dc.identifier.scopusid | 2-s2.0-85210272345 | - |
dc.identifier.url | www.mdpi.com/journal/electronics | - |
dc.subject.keyword | data deduplication | - |
dc.subject.keyword | distributed storage system | - |
dc.subject.keyword | fault tolerance | - |
dc.subject.keyword | scale-out storage | - |
dc.subject.keyword | write amplification | - |
dc.type.other | Article | - |
dc.description.isoa | true | - |
dc.subject.subarea | Control and Systems Engineering | - |
dc.subject.subarea | Signal Processing | - |
dc.subject.subarea | Hardware and Architecture | - |
dc.subject.subarea | Computer Networks and Communications | - |
dc.subject.subarea | Electrical and Electronic Engineering | - |
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