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RAPID: Redundancy Analysis With Parallelized and Intelligent Distributionoa mark
  • Yoo, Younwoo ;
  • Lee, Hayoung ;
  • Ho Shin, Seung ;
  • Kang, Sungho
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Publication Year
2025-01-01
Publisher
Institute of Electrical and Electronics Engineers Inc.
Citation
IEEE Access, Vol.13, pp.2089-2100
Keyword
Analysis timegraphics processing unit (GPU)memoryredundancy analysis (RA)repair rateyield
Mesh Keyword
Analysis methodAnalysis timeGraphic processing unitGraphics processingProcessing unitsRedundancy analysisRedundancy analyzeRepair rateSpare cellsYield
All Science Classification Codes (ASJC)
Computer Science (all)Materials Science (all)Engineering (all)
Abstract
The continuous progress in semiconductor technology, particularly in nanotechnology, has led to smaller memory cells and increased fault frequency due to their proximity. These faults reduce memory yield and raise production costs. Redundancy Analysis (RA) offers an effective solution by allocating spare cells within memory to repair faulty lines. The main goal of RA is to optimally place spare cells rapidly to achieve the highest repair rate, resulting in the development of various RA methods. In modern memory architectures, complex spare structures are essential for improving repair rates. However, traditional RA methods can be too time-consuming for such structures, limiting the repair of multiple memories. This paper proposes a method called RAPID, which leverages GPU technology for the parallel repair of multiple memories. RAPID generates repair cases by segmenting areas based on available spare types, ensuring efficient GPU memory use and enabling simultaneous repairs. Repair cases are applied immediately upon fault detection during testing, significantly reducing repair time. Experimental results show that RAPID can repair more memory units in less repair time than previous GPU-based RA methods under the same GPU and CPU memory specifications.
ISSN
2169-3536
Language
eng
URI
https://dspace.ajou.ac.kr/dev/handle/2018.oak/34687
DOI
https://doi.org/10.1109/access.2024.3523940
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Type
Article
Funding
This work was supported by K-CHIPS (Korea Collaborative & High-tech Initiative for Prospective Semiconductor Research) (RS-2023-00301703, 23045-15TC) funded by the Ministry of Trade, Industry & Energy (MOTIE, Korea) (1415188224).
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Lee, Hayoung이하영
Department of Intelligence Semiconductor Engineering
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