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Comparative analysis of junctionless and inversion-mode nanosheet FETs for self-heating effect mitigation
  • An, Do Gyun ;
  • Kim, Garam ;
  • Kim, Hyunwoo ;
  • Kim, Sangwan ;
  • Kim, Jang Hyun
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Publication Year
2024-01-01
Publisher
Institute of Physics
Citation
Semiconductor Science and Technology, Vol.39
Keyword
gate-all-around FEThigh temperaturejunctionlessnanosheet-FET (nsFET)self-heating effect (SHE)thermal characteristicszero-temperature coefficient (ZTC)
Mesh Keyword
Comparative analyzesField-effect transistorHighest temperatureJunctionlessNanosheet-FETSelf-heating effectThermal characteristicsZero temperature coefficientsZero-temperature coefficient
All Science Classification Codes (ASJC)
Electronic, Optical and Magnetic MaterialsCondensed Matter PhysicsElectrical and Electronic EngineeringMaterials Chemistry
Abstract
Artificial intelligence computing requires hardware like central processing units and graphic processing units for data processing. However, excessive heat generated during computations remains a challenge. The paper focuses on the heat issue in logic devices caused by transistor structures. To address the problem, the operational mechanism of the Junctionless Field-Effect Transistor (JLFET) is investigated. JLFET shows potential in mitigating heat-related issues and is compared to other nanosheet (ns) FETs. In the case of JL-nsFET, the change in mobility with increasing temperature is smaller compared to Con-nsFET, resulting in less susceptibility to lattice scattering and thermal resistance (Rth) in self-heating effect situation is 0.43 [K µW−1] for Con-nsFET and 0.414 [K µW−1] for JL-nsFET. The reason why the Rth of JL-nsFET is smaller than that of Con-nsFET is that JL-nsFET uses a source heat injection conduction mechanism and a large heat transfer area by using a bulk channel.
Language
eng
URI
https://dspace.ajou.ac.kr/dev/handle/2018.oak/33875
DOI
https://doi.org/10.1088/1361-6641/ad10c4
Fulltext

Type
Article
Funding
This work was supported by the National Research Foundation of Korea (NRF) grant funded by the Korean government (MSIT) (No. 2022R1A2C1093201). The EDA tool was supported by the IC Design Education Center (IDEC), KOREA.
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