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Effects of Material and Doping Profile Engineering of Source Junction on Line Tunneling FET Operations
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Publication Year
2023-08-01
Publisher
Institute of Electronics Engineers of Korea
Citation
Journal of Semiconductor Technology and Science, Vol.23, pp.228-235
Keyword
line tunneling FET (LTFET)on-off current ratio (ION/IOFF)partial light doping sourcepartial SiGe sourcesubthreshold swing (SS)Tunneling field-effect transistor (TFET)
Mesh Keyword
Line tunneling FETOn-off current ratio (ION/IOFF)ON/OFF current ratioOn/off-current ratiosPartial light doping sourcePartial sige sourceSub-threshold swing(ss)Subthreshold swingTunneling field-effect transistorTunneling field-effect transistors
All Science Classification Codes (ASJC)
Electronic, Optical and Magnetic MaterialsElectrical and Electronic Engineering
Abstract
—The electrical characteristics of line tunneling field-effect transistor (LTFET) is analyzed by technology computer-aided design (TCAD) simulation when the material and doping concentration at the end of the source junction are changed. Partial use of SiGe at the end of Ge source can reduce power consumption by reducing off-state current (IOFF) while maintaining on-state current (ION). In addition, if the doping concentration at the end of the source is lowered, ION is improved and electrical characteristics suitable for high performance applications can be obtained. But these two methods also have disadvantages. In the case of lowering doping concentration at the end of the source, IOFF is higher than conventional LTFET. In the case of Partial use of SiGe at the end of Ge source, ION is lower than conventional LTFET. However, combining these two methods can overcome each other’s disadvantages with the advantages of the other method.
ISSN
1598-1657
Language
eng
URI
https://dspace.ajou.ac.kr/dev/handle/2018.oak/33648
DOI
https://doi.org/10.5573/jsts.2023.23.4.228
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Type
Article
Funding
This work was supported by the National Research Foundation of Korea (NRF) grant funded by the Korea government. (MSIT) (2022R1A2C1093201) The EDA tool was supported by the IC Design Education Center (IDEC), Korea.
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Kim, Jang Hyun Image
Kim, Jang Hyun김장현
Department of Electrical and Computer Engineering
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