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The Significance of an In Situ ALD Al2O3 Stacked Structure for p-Type SnO TFT Performance and Monolithic All-ALD-Channel CMOS Inverter Applicationsoa mark
  • Kim, Hye Mi ;
  • Choi, Su Hwan ;
  • Lee, Han Uk ;
  • Cho, Sung Beom ;
  • Park, Jin Seong
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Publication Year
2023-04-01
Publisher
John Wiley and Sons Inc
Citation
Advanced Electronic Materials, Vol.9
Keyword
atomic layer depositioncomplementary metal–oxide–semiconductorp-type oxide semiconductorthin-film transistortin monoxide
Mesh Keyword
Atomic-layer depositionC. thin film transistor (TFT)Complementary metal oxide semiconductorsElectrical performanceMonolithicsP-type oxide semiconductorsp-Type SnOStacked structureTin monoxidesTransistor performance
All Science Classification Codes (ASJC)
Electronic, Optical and Magnetic Materials
Abstract
Tin monoxide (SnO) has been studied widely over the past several decades due to its promising theoretical p-type performance. However, limited fabrication processes due to the low thermal and air stability of SnO have resulted in poor performance in thin-film transistors (TFTs). Here, it is suggested that in situ atomic layer deposition (ALD) of an Al2O3 capping layer can improve the electrical performance in SnO TFTs. By adopting an in situ stacking process, which protects vulnerable SnO thin films from exposure to air and contamination, SnO exhibits enhanced crystallinity, electrical performance, and improved scaling limitation of channel thickness. Especially, in situ stacked Al2O3 on a 7 nm SnO TFT has an exceptionally low subthreshold swing (0.15 V decade−1), high on/off ratio (6.54 × 105), and reasonable mobility (1.14 cm2 V−1 s−1) while the bare SnO TFT is not activated. Computational thermodynamics such as chemical potential analysis, nucleation Gibbs free-energy calculations, and various analytical techniques are used to reveal the origin of highly crystallized SnO formations via in situ deposition of Al2O3. Finally, state-of-the-art all-ALD-channel complementary metal–oxide–semiconductor inverters using n-type indium gallium zinc oxide and p-type SnO TFTs are integrated, which exhibit a maximum voltage gain of 240 V V−1 and a noise margin of 89.3%.
ISSN
2199-160X
Language
eng
URI
https://dspace.ajou.ac.kr/dev/handle/2018.oak/33301
DOI
https://doi.org/10.1002/aelm.202201202
Type
Article
Funding
H.\u2010M.K. and S.\u2010H.C. contributed equally to this work. This research was supported by the National Research Foundation of Korea (NRF) funded by the Ministry of Science and ICT (NRF\u20102020M3H4A3081867). This research used data obtained from XPS and XRD devices installed at Hanyang Linc+ Analytical Equipment Center (Seoul). The simulation was supported by the resource of National Supercomputing Center (KSC\u20102021\u2010RND\u20100042).
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Cho, Sung Beom  Image
Cho, Sung Beom 조성범
Department of Materials Science Engineering
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