This paper proposes an improved offset selection method for discontinuous-pulse-width-modulation (DPWM)-based back-to-back converters to reduce dc-link current ripple. DPWM is introduced to power converters to diminish the stress on power transistors and prolong their lifespan. However, when using the DPWM method, the dc-link current ripple is increased in nonswitching regions of the power transistors. Moreover, in DPWM-based back-to-back converters, the dc-link current ripple reaches its maximum when the two transistors of both inverters are clamped in opposite directions. Therefore, the dc-link capacitors endure more stress, resulting in decreased life duration. To overcome this issue, the switching method should consider the clamping periods, when the current ripple increases. This can be achieved by modifying the DPWM offset, so that the clamping states of both converters are matched. The effectiveness of the proposed method is confirmed by both simulation and experimental results.
Manuscript received January 10, 2017; revised April 30, 2017 and July 6, 2017; accepted August 6, 2017. Date of publication August 25, 2017; date of current version December 15, 2017. This work was supported in part by the Korea Institute of Energy Technology Evaluation and Planning (KETEP) and the Ministry of Trade, Industry & Energy (MOTIE) of the Republic of Korea (No. 20174030201660), and in part by the Basic Science Research Program through the National Research Foundation of Korea (NRF) funded by the Ministry of Science, ICT & Future Planning (No. 2016R1A2B4010636). (Corresponding author: Kyo-Beum Lee.) A. Tcai and K.-B. Lee are with the Department of Electrical and Computer Engineering, Ajou University, Suwon 443-749, South Korea (e-mail: anatolii.tcai@gmail.com; kyl@ajou.ac.kr).
