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Homogeneous ZrO2 gate dielectrics with intermediate ozone oxidation for improved interface stability and leakage suppression in Ge-based MOS devices
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Publication Year
2025-06-15
Journal
Materials Science in Semiconductor Processing
Publisher
Elsevier Ltd
Citation
Materials Science in Semiconductor Processing, Vol.192
Keyword
Germanium oxideHigh-k/Ge MOSOzone post oxidationZrO2
Mesh Keyword
Germaniums (Ge)High- kHigh-k/ge MOSInterface stabilitiesInterface trap densityInterface-trap densityOzone oxidationOzone post oxidationPost-oxidationZrO 2
All Science Classification Codes (ASJC)
Materials Science (all)Condensed Matter PhysicsMechanics of MaterialsMechanical Engineering
Abstract
With recent advances in semiconductor technology, Ge has gained significant attention as a high-mobility channel material. However, integrating Ge with high-k dielectrics remains challenging owing to the formation of unstable Ge suboxides at the interface, which degrade the device performance by increasing the interface trap density and leakage current. This study explores the use of a ZrO2 interlayer, replacing Al2O3, followed by ozone post-oxidation (OPO) and an additional ZrO2 deposition to create a homogeneous ZrO2 gate dielectric on Ge. The resulting ZrO2/OPO/ZrO2 structure effectively suppresses the formation of unstable Ge suboxides, blocks Ge diffusion, and reduces the number of polycrystalline ZrO2 phases. These advantages have been confirmed through extensive material studies including high-resolution transmission electron microscopy, X-ray photoelectron spectroscopy, and X-ray diffraction. The electrical characteristics were examined using capacitance-voltage and current density-voltage measurements. Moreover, the leakage current behavior was further analyzed using current conduction mechanism models. The ZrO2/OPO/ZrO2 stack exhibits a low equivalent oxide thickness (EOT) of 1.87 nm, an interface trap density (Dit) of 2.48 × 1012 cm−1ev−1, and a reduced leakage current density of 7.05 × 10−7 A/cm2 at 1 V. This study highlights the possibility of the ZrO2/OPO/ZrO2 stack as a high-performance gate dielectric for next-generation Ge-based MOS devices.
Language
eng
URI
https://aurora.ajou.ac.kr/handle/2018.oak/38530
https://www.scopus.com/inward/record.uri?partnerID=HzOxMe3b&scp=85219500631&origin=inward
DOI
https://doi.org/10.1016/j.mssp.2025.109435
Journal URL
https://www.sciencedirect.com/science/journal/13698001
Type
Article
Funding
This study was supported by the National R&D Program through the National Research Foundation of Korea (NRF) funded by the Ministry of Science and ICT (2020M3F3A2A01082593), and by the Industrial Strategic Technology Development Program (20020830) funded by the Ministry of Trade, Industry, and Energy (MOTIE, Korea).
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Heo, Junseok허준석
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