Soft-errors and aging are considered as two primary factors affecting the long-term reliability of aerospace integrated circuits (ICs). As one of the key components in aerospace ICs, latches play a pivotal role to ensure desirable circuit functionality. This paper presents a single-event-upset recovery latch, namely SRBML, with bias-temperature-instability (BTI)-mitigation. By optimizing its internal structure, the latch can recover from single-event-upsets (SEUs) and reduce the stress time of transistors in feedback loops to simultaneously mitigate the impact of BTI on the latch. Simulation results demonstrate that the soft error rate increase due to BTI is reduced by roughly 34% for SRBML after BTI-mitigation. In addition, the delay of SRBML is not affected, and the area and power increase are limited compared to BTI-unmitigated latches.
