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A 92 F2/ bit Physically Unclonable Function Exploiting Channel Charge Injection and Mismatch Accumulation
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Publication Year
2023-01-01
Journal
Proceedings of the Custom Integrated Circuits Conference
Publisher
Institute of Electrical and Electronics Engineers Inc.
Citation
Proceedings of the Custom Integrated Circuits Conference, Vol.2023-April
Mesh Keyword
Access pointsChallenge-response pairChannel chargeClassifiedsCritical metricsEnergy efficientHeuristic learningPhysically unclonable functionsSecurity attacksTemperature variation
All Science Classification Codes (ASJC)
Electrical and Electronic Engineering
Abstract
In the deployment of millions of edge devices connected via Internet of Things (loT), each of those devices are exposed as access points for security attacks. As a primitive solution to breaches, physical unclonable functions (PUF) are considered as one of the most cost/energy-efficient approaches providing hardware-oriented randomness, uniqueness, and reliability. PUF can be fundamentally classified into strong and weak PUFs. Strong PUFs can generate a large number of challenge-response pairs (CRPs) according to the given secret. However, due to the correlation between CRPs, it is vulnerable to attacks through the heuristic learning. On the other hand, weak PUFs typically produce a relatively small number of CRPs. Therefore, not only ideal uniqueness and stable response against voltage/temperature variations are important, but also efficient PUF cell area per bit (.F2 / bit) is a critical metric for weak PUFs to produce a large number of CRPs with high density.
ISSN
0886-5930
Language
eng
URI
https://aurora.ajou.ac.kr/handle/2018.oak/36939
https://www.scopus.com/inward/record.uri?partnerID=HzOxMe3b&scp=85160012099&origin=inward
DOI
https://doi.org/10.1109/cicc57935.2023.10121230
Type
Conference
Funding
Fig. 5 (top) shows the intra-/inter-HD of the proposed PUF. The statistical distribution of HD for the 3T/4T PUF cells show close-to-ideal values. For the 4T PUF cell, the ratio of distinguishableness between the HDs is 80.54\u00d7 with 0% masking, which largely increases to 2,780\u00d7 with a low masking ratio of 2.5% and TMV11 stabilization. Fig. 5 (bottom) shows the measured autocorrelation coefficient of 0.0119 (95% CI), which we achieve with 37.2 Mbps throughput and 0.0106 pJ/bit core energy efficiency (energy breakdown from post-layout simulation shows 59.2%, 30.7%, and 10.1% are consumed by BL/BLB pre-charge, Dcomp, and decoder, respectively). We verified 15 chips with NIST 800-22 randomness sub-tests (Fig. 5). Fig. 6 show the comparison with state-of-the-art PUF works. The proposed PUF demonstrates 2.37\u00d7 higher area efficiency than the state-of-the-art while consuming low energy, due to its simple structure, novel charge injection/ accumulation scheme, and CMS, without complex peripheral circuitry. Acknowledgement: This work is partially supported by NSF grant 1652866. References: [1] J. Park et al., ISSCC, 2021. [2] K. Yang et al., ISSCC, 2017. [3] K. Liu et al., JSSC, 2020. [4] Y. He et al., ISSCC, 2021. [5] J. Lee et al., ISSCC, 2018. [6] M.-Y. Wu et al., ISSCC, 2018.
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 Jee, Dong Woo Image
Jee, Dong Woo지동우
Department of Electrical and Computer Engineering
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