In this study, we rethink the existing memory placement strategies for multi-chip server systems. Processor vendors such as Intel and AMD have introduced the multi-chip based high density server architecture for large-scale data centers. With the advance of the processor-interconnect, multiple CPU chips are connected through a scalable point-to-point network such as Intel UPI and AMD Infinity Fabric. Nevertheless, the existing operating systems including Linux do not fully take advantage of the processor-interconnect to manage the memory traffic across memory nodes. We present two memory placement techniques exploiting the point-to-point interconnect to improve overall throughput while minimizing the hot-spot problem.
We thank our anonymous reviewers for their invaluable comments. This work was supported by the National Research Foundation of Korea (NRF) grant funded by the Korea government (MSIT) (NRF-2019R1C1C1005166).
