This paper introduces a method to reduce circulating current with high frequency in parallel inverters. The high frequency component of circulating current is generated by output voltage discrepancy of each inverter module in parallel. When inverter modules are connected in parallel and have individual digital controller, the multiple carriers for PWM cannot be synchronized without special compensation method. The traditional compensation method is based on carrier synchronization by additional communication or reference signal. However, the existing compensation methods are increasing system complexity and maintenance cost. This paper proposes an improved reduction method by adjusting carrier's period according to the magnitude of zero sequence current. The proposed method can be implemented only by adding S/W code. The characteristics of circulating current due to phase difference between carries is also analyzed. The proposed method is verified by PSIM simulation.
This work was supported bytheKorea Instituteof EnergyTechnology Evaluationand Planning (KETEP) grant fundedbytheKorea government (MOTIE) (No.20182410105160, Demonstration and Development of ESS SolutionConnectedwithRenewable Energy againstwiththeweather condition ofMiddleEast Region)
