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Self-Aligned Edge Contact Process for Fabricating High-Performance Transition-Metal Dichalcogenide Field-Effect Transistors
  • Ko, Seokjin ;
  • Lee, Dongryul ;
  • Kim, Jeongmin ;
  • Kim, Chang Koo ;
  • Kim, Jihyun
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Publication Year
2024-09-10
Journal
ACS Nano
Publisher
American Chemical Society
Citation
ACS Nano, Vol.18 No.36, pp.25009-25017
Keyword
edge contactFermi-level pinninggate spacermobilityself-aligned fabricationtransition metal dichalcogenide
Mesh Keyword
Contact processEdge contactsFermi level pinningField-effect transistorGate spacersMobilityPerformanceSelf aligned fabricationSelf-alignedTransition metal dichalcogenides (TMD)
All Science Classification Codes (ASJC)
Materials Science (all)Engineering (all)Physics and Astronomy (all)
Abstract
The persistent challenges encountered in metal-transition-metal dichalcogenide (TMD) junctions, including tunneling barriers and Fermi-level pinning, pose significant impediments to achieving optimal charge transport and reducing contact resistance. To address these challenges, a pioneering self-aligned edge contact (SAEC) process tailored for TMD-based field-effect transistors (FETs) is developed by integrating a WS2 semiconductor with a hexagonal boron nitride dielectric via reactive ion etching. This approach streamlines semiconductor fabrication by enabling edge contact formation without the need for additional lithography steps. Notably, SAEC TMD-based FETs exhibit exceptional device performance, featuring a high on/off current ratio of ∼108, field-effect mobility of up to 120 cm2/V·s, and controllable polarity─essential attributes for advanced TMD-based logic circuits. Furthermore, the SAEC process enables precise electrode positioning and effective minimization of parasitic capacitance, which are pivotal for attaining high-speed characteristics in TMD-based electronics. The compatibility of the SAEC technique with existing Si self-aligned processes underscores its feasibility for integration into post-CMOS applications, heralding an upcoming era of integration of TMDs into Si semiconductor electronics. The introduction of the SAEC process represents a significant advancement in TMD-based microelectronics and is poised to unlock the full potential of TMDs for future electronic technologies.
ISSN
1936-086X
Language
eng
URI
https://aurora.ajou.ac.kr/handle/2018.oak/34401
https://www.scopus.com/inward/record.uri?partnerID=HzOxMe3b&scp=85201783942&origin=inward
DOI
https://doi.org/10.1021/acsnano.4c06159
Journal URL
http://pubs.acs.org/journal/ancac3
Type
Article
Funding
This work was supported by the Korea Research Institute for Defense Technology Planning and Advancement (KRIT) grant funded by the Defense Acquisition Program Administration (DAPA) (KRIT-CT-21-034) and the Technology Innovation Program (RS-2023-00267003), funded By the Ministry of Trade, Industry & Energy (MOTIE, Korea).
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Kim, Chang-Koo김창구
Department of Chemical Engineering
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