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Surface Modification and Theoretical Investigation by Simulation for Light Trapping in Silicon Heterojunction Solar Cells
  • Park, Hyeong Gi ;
  • Shin, Myunghun ;
  • Kim, Yong Ki ;
  • Lee, Jae Hyun ;
  • Ju, Minkyu ;
  • Yi, Junsin
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Publication Year
2023-12-01
Journal
Transactions on Electrical and Electronic Materials
Publisher
Korean Institute of Electrical and Electronic Material Engineers
Citation
Transactions on Electrical and Electronic Materials, Vol.24 No.6, pp.579-588
Keyword
Heterojunction solar cellHigh efficiencyLight trappingSurface modification
Mesh Keyword
Cell-beCell/B.EHeterojunction solar cellsHigher efficiencyLight-trappingRear sideSilicon heterojunctionsSurface-modificationTheoretical investigationsThin wafers
All Science Classification Codes (ASJC)
Electronic, Optical and Magnetic MaterialsElectrical and Electronic Engineering
Abstract
The 25% conversion efficiency of silicon solar cells is attributed to monocrystalline silicon wafers. These wafers have been utilized in the development of heterojunction with intrinsic thin-layer solar cells. To harness electrical power efficiently from a solar cell, it is essential not only to enhance its performance but also to significantly reduce its production costs. It is projected that the thickness of the Si wafer will gradually approach a minimum value of approximately 100 μm in the future. As a result, reducing the as-cut wafer thickness can lead to a more efficient utilization of silicon. In this paper, we present an approach for surface modification using a thin wafer, specifically for the application of rear-emitter silicon heterojunction (RE-SHJ) solar cells. RE-SHJ solar cells often experience a reduction in current density due to optical losses, such as the absorption in each layer and reflections on both the front and rear sides. For the application of RE-SHJ solar cells, we fabricated different pyramid sizes using a texturing solution after polishing the rear surface. The surface modifications in this study incorporated both front-side texturing and rear-side polishing. These modifications can contribute to enhanced efficiency, even with a thin wafer.
ISSN
2092-7592
Language
eng
URI
https://aurora.ajou.ac.kr/handle/2018.oak/33720
https://www.scopus.com/inward/record.uri?partnerID=HzOxMe3b&scp=85173949365&origin=inward
DOI
https://doi.org/10.1007/s42341-023-00479-z
Journal URL
https://www.springer.com/journal/42341
Type
Article
Funding
This research was supported by Korea Initiative for fostering University of Research and Innovation Program of the National Research Foundation (NRF) funded by the Korean government (MSIT) (Nos. NRF2021M3H1A104892211, 2021R1A2C2012649).
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