Ajou University repository

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Showing results 1 to 10 of 1063 (Search time: 0.0 seconds).

An Area-Efficient Systolic Array Redundancy Architecture for Reliable AI Accelerator
  • 2024-01-01
  • IEEE Transactions on Very Large Scale Integration (VLSI) Systems, Vol.32, pp.1950-1954
  • Institute of Electrical and Electronics Engineers Inc.
Convolution Neural Networks를 위한 고속 Convolution 알고리즘 과 가속기
  • 김태선
  • 2019-02
  • The Graduate School, Ajou University
Robust high-multiplication factor MDLL using IIR filter-based accumulated jitter reductionoa mark
  • 2018-06-14
  • Electronics Letters, Vol.54, pp.743-744
  • Institution of Engineering and Technology
Reconciling Output and Unemployment Fiscal Multipliers
  • 2019-10-02
  • Global Economic Review, Vol.48, pp.378-395
  • Routledge
Secure sharing scheme of sensitive data in the precision medicine systemoa mark
  • 2020-06-30
  • Computers, Materials and Continua, Vol.64, pp.1527-1553
  • Tech Science Press
A DLL based clock multiplier using rotational DCDL and PRNG for spur reductionoa mark
  • 2019-01-01
  • IEICE Electronics Express, Vol.16
  • Institute of Electronics Information Communication Engineers
심층 신경망을 위한 Skip 알고리즘 이용하는Convolution 가속기
  • 김영호
  • 2018-02
  • The Graduate School, Ajou University
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