A high-multiplication factor multiplying delay-locked loop (MDLL) with infinite impulse response filter-based accumulated jitter reduction technique is presented. In every output clock cycle, the proposed jitter reduction loop samples the periodic jitter, accumulates it, and subtracts accumulated jitter from the next output clock period. The proposed technique is applied to 10 MHz MDLL with 32 kHz reference clock, a multiplication factor of 313, shows 38% jitter reduction, and greatly improves MDLL locking even with high-supply noise. The MDLL implemented in 0.18 ìm CMOS process consumes 42 ìW and the core area is 0.043 mm2.
Acknowledgments: This work was supported by and the National Research Foundation of Korea grant funded by the Korea government (No. 2015R1C1A1A01051634). The chip fabrication and EDA tool were supported by IDEC, Korea.
