An algorithmic pattern generator (ALPG) has been developed within automatic test equipment (ATE) due to the extensive number of test patterns required for testing the memories. Since shared-resource ALPG generates the test pattern using the same arithmetic instruction and timing across multiple input/output (I/O) pins, the maximum operating frequency is limited by the delay of the arithmetic operation. On the other hand, per-pin ALPG can achieve high-speed operations by generating one bit of the test pattern for each I/O pin. However, the hardware cost is significantly increased due to the need for individual instruction and pattern generator (PG) for each I/O pin. To address these limitations, a cost-effective per-pin ALPG for high-speed memory testing is proposed. The proposed per-pin ALPG can achieve high-speed operations, and the hardware resources for storing and decoding the instructions are shared among multiple I/O pins to reduce the hardware cost. The experimental results indicate that the proposed ALPG can achieve a higher speed than the conventional per-pin ALPG with a reasonable hardware cost comparable to the conventional shared-resource ALPG.
Received 19 July 2024; revised 15 September 2024; accepted 22 October 2024. This work was supported in part by the Ministry of Trade, Industry and Energy (MOTIE) under Grant 20019363; and in part by Korea Semiconductor Research Consortium (KSRC) support Program for the Development of the Future Semiconductor Device. (Corresponding author: Sungho Kang.) mentof Electricaland ElectronicEngineering,YonseiUniversity,SeoulJuyongLee, SooryeongLee, andSungho KangarewiththeDepart- As depicted in Fig. 1, the shared-resource ALPG comprises shared 03722, South Korea (e-mail: jdra@yonsei.ac.kr; leeth95@yonsei.ac.kr; hardware resources for multiple I/O pins, such as the instruction shkang@yonsei.ac.kr). memory, the sequence controller, the timing generator, and the PG. Hayoung Lee is with the Department The PG consists of an address generator, a data generator, and tor Engineering, Ajou University, Suwon a control generator. The execution of arithmetic instructions using Color versions of one or more figures inhyleee@ajou.ac.kr). ALUs within the address generator and the data generator results https://doi.org/10.1109/TVLSI.2024.3486332. in address and data patterns for the MUT. The control signals for Digital Object Identifier 10.1109/TVLSI.2024.3486332 read and write operations on the MUT are generated by the control 1063-8210 \\u00A9 2024 IEEE. Personal use is permitted, but republication/redistribution requires IEEE permission. See https://www.ieee.org/publications/rights/index.html for more information.
