Optimizing De-Trap Pulses in Gate-Injection Type Ferroelectric NAND Cells to Minimize Read after Write Delay Issue

Abstract

The ferroelectric (FE) NAND flash, featuring metal-interlayer-FE-interlayer-silicon (MIFIS) gate stacks, leverages both charge trapping and polarization (P) switching to achieve a broad memory window (MW) and low operation voltage. These remarkable advancements establish it as a viable contender for future NAND flash technologies. However, the read-after-write-delay (RAWD) problem during program/erase (PGM/ERS), caused by channel-injected interface trapped charges (Qit) between the FE layer and the channel interlayer (Ch.IL), leading to short-term Vth variations, remains unexplored in MIFIS FE-NAND cells. This letter presents the first analysis of RAWD in FE-NAND cells, including the experimental optimization of a de-trap pulse that effectively eliminates Qit whereas preserving both gate-injected interface trapped charges (Qit') and P. Consequently, the FE-NAND cell exhibits a narrow MW of 3.45 V at a delay time (tDelay) of 1 μs between PGM/ERS and read operations, expending to 7.40 V at a tDelay of 1 s. This variation is attributed to the generation of Qit and the subsequent de-trap process, affecting channel conductivity. To thoroughly address the RAWD, various pulse widths and amplitudes are experimentally explored immediately post-PGM/ERS to optimize the de-trap pulse for selective Qit removal. Upon applying the optimized detrap pulse, the stable wide MW (7.40 V) is consistently maintained regardless of tDelay. This work is meaningful as it brings attention to previously unexplored issues in next-generation ferroelectric (FE) NAND cells and suggests practical operational solutions.