A 48×2 CMOS SPAD Sensor With Regulated Dark Count

Abstract

This brief presents a dark count regulation technique for CMOS SPAD array sensor. Proposed global/local dual biasing scheme allows setting an individual excess bias for each SPAD. The column shared calibration block compares each pixel's dark count to a target count value to control the local bias voltage of that pixel. The 48\times 2 SPAD sensor chip is implemented in a 0.18~\mu \text{m} BCD CMOS process and the proposed technique improves the dark count uniformity by \times 2.6. We also demonstrated the linear control of photon detection efficiency as well as the average dark count of the sensor.