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High Efficiency and Low Complexity Dual-Reference Voltage-Based Pulse Width Modulation for Three-Phase Five-Level HANPC Inverters
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Publication Year
2024-07-01
Publisher
Korean Institute of Electrical Engineers
Citation
Journal of Electrical Engineering and Technology, Vol.19, pp.3047-3057
Keyword
Digital signal processor (DSP)Dual-reference voltageFive-level hybrid active neutral-point-clamped (HANPC) invertersPhase shifted carrier pulse width modulation (PSC-PWM)Thermal losses balancingTime-delay
Mesh Keyword
Active neutral point clampedCarrier pulseDigital signal processorDual-reference voltageFive-level hybrid active neutral-point-clamped inverterNeutral-point clamped invertersPhase shiftedPhase shifted carrier pulse width modulationPulsewidth modulations (PWM)Reference voltagesThermal lossThermal loss balancingTime-delays
All Science Classification Codes (ASJC)
Electrical and Electronic Engineering
Abstract
This study proposes a low complex and high efficient dual-reference voltage-based pulse width modulation (DRV-PWM) scheme for three-phase five-level hybrid active neutral-point-clamped (HANPC) inverters. Although phase-shifted carrier PWM (PSC-PWM) is capable of naturally balancing dc-link and flying capacitors voltages, such a process requires a tedious and sophisticated adjustment of the phase-shift between the PWM signals, particularly in a digital signal processor (DSP). As a result, a phase-delay eventually occurs, which leads to unevenly distributed thermal losses among the three phases of the five-level HANPC inverter. Therefore, this study introduces an alternative switching scheme that has the same merits as the conventional PSC-PWM in naturally balancing the voltages without requiring voltage sensors. It also balances the thermal losses across the three phases, which enhances the reliability and efficiency of the switching devices. The proposed DRV-PWM is experimentally evaluated in comparison to conventional PSC-PWM on a TMS320F28377S DSP. The experimental results reveal that the proposed DRV-PWM effectively synchronizes the execution of the three-phase pole voltages while also keeping the thermal losses evenly distributed among the three phases.
Language
eng
URI
https://dspace.ajou.ac.kr/dev/handle/2018.oak/33862
DOI
https://doi.org/10.1007/s42835-023-01763-x
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Type
Article
Funding
This work was supported in part by the Korea Institute of Energy Technology Evaluation and Planning (KETEP) and the Ministry of Trade, Industry & Energy (MOTIE) of the Republic of Korea under Grant 20206910100160 and Grant 20225500000110.
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Lee, Kyo-Beum이교범
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