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A comparative study of charge trapping effect in p-type MoTe2 and WSe2 FETs using pulsed current-voltage measurements
  • Yang, Jeong Yong ;
  • Lee, Chan Ho ;
  • Oh, Young Taek ;
  • Ma, Jiyeon ;
  • Heo, Junseok ;
  • Yoo, Geonwook
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Publication Year
2021-01-01
Publisher
IOP Publishing Ltd
Citation
Japanese Journal of Applied Physics, Vol.60
Mesh Keyword
Charge trapping effectComplementary metal oxide semiconductorsElectrical characteristicField-effect mobilitiesMolybdenum ditelluridePulsed current voltagePulsed current-voltage measurementTwo Dimensional (2 D)
All Science Classification Codes (ASJC)
Engineering (all)Physics and Astronomy (all)
Abstract
P-type semiconductors are indispensable for achieving complementary metal oxide semiconductor and integrated circuits based on two-dimensional (2D) semiconductors, and tungsten diselenide (WSe2) and molybdenum ditelluride (MoTe2) are the promising channel materials for PMOS. In this work, we report on the charge trapping effects on hysteretic behavior and field-effect mobility (μFE) of the p-type WSe2 and MoTe2 FETs using fast pulsed current-voltage (I-V) measurements. The hysteresis is reduced by nearly 98% via ramped pulsed measurements, and μFE is significantly enhanced via single pulse measurements by minimizing the charge trapping. Moreover, WSe2 FETs are found to be more susceptible to the charge trapping effects compared with MoTe2 FETs; WSe2 FETs exhibit more pronounced enhancement of μFE and reduction of hysteresis. The intrinsic electrical characteristics of p-type 2D FETs under minimized charge trapping conditions can be investigated using the pulsed I-V characterizations.
Language
eng
URI
https://dspace.ajou.ac.kr/dev/handle/2018.oak/31771
DOI
https://doi.org/10.35848/1347-4065/abd6d5
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Type
Article
Funding
This work was supported by the Industrial Strategic Technology Development Program (20000300) and the Korea Institute for Advancement of Technology under the Competency Development Program (N0001883) funded by the Ministry of Trade, Industry and Energy (MOTIE, Korea). The EDA tool was supported by the IC Design Education Center(IDEC), Korea.
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