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Improved Switched-Capacitor Integrated Multilevel Inverter with a DC Source String
  • Lee, Sze Sing ;
  • Lee, Kyo Beum ;
  • Alsofyani, Ibrahim Mohd ;
  • Bak, Yeongsu ;
  • Wong, Jing Fang
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Publication Year
2019-11-01
Publisher
Institute of Electrical and Electronics Engineers Inc.
Citation
IEEE Transactions on Industry Applications, Vol.55, pp.7368-7376
Keyword
Circuit topologydc-ac power conversionhigh voltage gainmultilevel inverterswitched-capacitor
Mesh Keyword
DC-AC power conversionHigh voltage gainHigh-voltage stressMultilevel inverterOperational analysisSwitched -capacitor circuitsSwitched capacitorSwitched capacitor techniques
All Science Classification Codes (ASJC)
Control and Systems EngineeringIndustrial and Manufacturing EngineeringElectrical and Electronic Engineering
Abstract
The integration of switched-capacitor techniques into multilevel inverters (MLIs) with a dc source string contributes to the boosting of voltage gain, renders it particularly attractive in reducing the number of input dc sources in the series string. However, the recent two-stage MLI topologies suffer from high voltage stress across the backend H-bridge. Addressing this concern, an improved topology, namely the one-switched-capacitor integrated MLI (1SCI-MLI) is proposed in this paper. An extended topology of 1SC-MLI is also established by appropriate incorporation of another switched-capacitor circuit. The two proposed topologies are endowed with voltage boosting capability. They also feature low switch count and low number of dc sources. More importantly, they resolve the high voltage stress problem in the existing counterparts. Their corresponding operational analysis and comparisons with recent MLI topologies are discussed. Simulation and experimental results from a laboratory prototype are presented to validate the effectiveness of the proposed topologies.
Language
eng
URI
https://dspace.ajou.ac.kr/dev/handle/2018.oak/31026
DOI
https://doi.org/10.1109/tia.2019.2893850
Fulltext

Type
Article
Funding
This work was supported in part by the KEPCO Research Institute under the project entitled Design of analysis model and optimal voltage for MVDC distribution system (R17DA10), in part by the Korea Foundation for Advanced Studies under International Scholar Exchange Fellowship, and in part by the Malaysian Ministry of Higher Education under Fundamental Research under Grant FRGS/1/2018/TK04/USMC/02 /1.Manuscript received September 14, 2018; revised December 28, 2018; accepted January 13, 2019. Date of publication January 17, 2019; date of current version November 7, 2019. Paper 2018-HPC-0965.R1, approved for publication in the IEEE TRANSACTIONS ON INDUSTRY APPLICATIONS by the High Performance Power Electronic Converters: Topologies, Control, and Devices Committee of the IEEE Industry Applications Society. This work was supported in part by the KEPCO Research Institute under the project entitled “Design of analysis model and optimal voltage for MVDC distribution system” (R17DA10), in part by the Korea Foundation for Advanced Studies under International Scholar Exchange Fellowship, and in part by the Malaysian Ministry of Higher Education under Fundamental Research under Grant FRGS/1/2018/TK04/USMC/02 /1. (Corresponding author: Sze Sing Lee.) S. S. Lee is with the Department of Electronics and Computer Science, University of Southampton Malaysia, Johor Bahru 79200, Malaysia, and also with the Power Electronics Laboratory, Ajou University, Suwon 16499, South Korea (e-mail:,szesinglee@gmail.com).Dr. Lee received the International Scholar Exchange Fellowship from Korea Foundation for Ad-
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