Ajou University repository

IEEE Transactions on Very Large Scale Integration (VLSI) Systems
ISSN
  • E1557-9999
  • P1063-8210
Publisher

Institute of Electrical and Electronics Engineers

Listed on
(Coverage)

JCR1997-2023

SJR1999-2020;2022-2023

CiteScore2011-2023

SCIE2010-2024

CC2016-2024

SCOPUS2017-2024

Active
Active

based on the information

  • SCOPUS:2024-10
Country
USA
Aime & Scopes
Design and realization of microelectronic systems using VLSI/ULSI technologies requires close collaboration among scientists and engineers in the fields of systems architecture, logic and circuit design, chips and wafer fabrication, packaging, testing, and systems applications. Generation of specifications, design, and verification must be performed at all abstraction levels, including the system, register-transfer, logic, circuit, transistor, and process levels. To address this critical area through a common forum, the IEEE Transactions on VLSI Systems was founded. The editorial board, consisting of international experts, invites original papers which emphasize the novel system integration aspects of microelectronic systems, including interactions among system design and partitioning, logic and memory design, digital and analog circuit design, layout synthesis, CAD tools, chips and wafer fabrication, testing and packaging, and system level qualification. Thus, the coverage of this Transactions focuses on VLSI/ULSI microelectronic system integration. Topics of special interest include, but are not strictly limited to, the following: • System Specification, Design and Partitioning, • System-level Test, • Reliable VLSI/ULSI Systems, • High Performance Computing and Communication Systems, • Wafer Scale Integration and Multichip Modules (MCMs), • High-Speed Interconnects in Microelectronic Systems, • VLSI/ULSI Neural Networks and Their Applications, • Adaptive Computing Systems with FPGA components, • Mixed Analog/Digital Systems, • Cost, Performance Tradeoffs of VLSI/ULSI Systems, • Adaptive Computing Using Reconfigurable Components (FPGAs)
Article List

Showing results 1 to 4 of 4

Effective Parallel Redundancy Analysis Using GPU for Memory Repair
  • 2025-01-01
  • IEEE Transactions on Very Large Scale Integration (VLSI) Systems, Vol.33 No.2, pp.462-474
  • Institute of Electrical and Electronics Engineers Inc.
An Area-Efficient Systolic Array Redundancy Architecture for Reliable AI Accelerator
  • 2024-01-01
  • IEEE Transactions on Very Large Scale Integration (VLSI) Systems, Vol.32 No.10, pp.1950-1954
  • Institute of Electrical and Electronics Engineers Inc.
An Efficient Test Architecture Using Hybrid Built-In Self-Test for Processing-in-Memory
  • 2024-01-01
  • IEEE Transactions on Very Large Scale Integration (VLSI) Systems
  • Institute of Electrical and Electronics Engineers Inc.
A Cost-Effective Per-Pin ALPG for High-Speed Memory Testing
  • 2024-01-01
  • IEEE Transactions on Very Large Scale Integration (VLSI) Systems
  • Institute of Electrical and Electronics Engineers Inc.
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