ICLTR: A Input-split Inverters and C-elements based Low-Cost Latch with Triple-Node-Upset Recovery

Abstract

As the semiconductor technology continues to advance, integrated circuits (ICs) are becoming increasingly sensitive to soft errors, e.g., double-node upsets (DNUs) and triplenode upsets (TNUs), induced by harsh radiation. In this paper, a low-cost latch design, namely ICLTR, using input-split inverters (ISIs) and C-elements to provide complete TNU recovery, is proposed. ICLTR consists of seven ISIs, seven 2-input C-elements and a clock-gated inverter, and all these elements are interlocked. Simulation results show the complete TNU recovery for ICLTR. The simulation results also show that ICLTR can save 59.5% of the transmission delay, 36.1% of the power consumption and 81.6% of the delay-area-power product (DAPP) on average when compared with the same type of TNU recovery latch designs.