APOD PWM Based Method to Suppress Zero-Sequence Circulating Current in Parallel Three-Level NPC Inverters under Interleaved Operation

Abstract

This paper presents a method to reduce high-frequency (HF) and low-frequency (LF) zero-sequence circulating current (ZSCC) simultaneously under the interleaved operating conditions. Recently, a parallel operation of inverters has been widely used to obtain high power ratings. A parallel operation degrades the quality of the output current because the current harmonics of each inverter overlap. While the interleaved operation prevents the increment of the current harmonics, HF-ZSCC generated by intentional carrier phase difference is inevitable. The carrier modulation method using the alternative phase opposition disposition pulse width modulation (APOD PWM) is effective to reduce ZSCC generated by the interleaved PWM. In this paper, both the double-reference PWM (DRPWM) method and the optimized zero-sequence voltage (ZSV) injection method based on APOD PWM are used to reduce HF- and LF-ZSCC respectively. The feasibility and effectiveness of the proposed method are verified by simulation results.