A reliability improvement method for three-level inverters with modified VSVPWM

Abstract

This paper proposes a novel virtual space vector pulse width modulation (VSVPWM) method for reliability improvement of the three-level inverters. In the three-level inverters, the DC-link is divided into two capacitors to create the neutral-point (NP). The split DC-link capacitors induce a drawback which is AC unbalance between each DC-link voltage of capacitors. To mitigate this drawback, VSVPWM was widely researched. The VSVPWM controls AC ripple component of the NP voltage to zero within one switching period. However, VSVPWM does not consider the NP ripple current and CMV. The NP current equals to the sum of each capacitor currents. Its large ripple component increases the core temperature in capacitor, which reduces the lifespan of the DC-link capacitors. Additionally, CMV with a large peak-to-peak value generates the electro-magnetic interference issues and leakage current. In this paper, an optimized VSVPWM for suppressing the capacitor ripple current and the variation of CMV is proposed. The effectiveness and validity of the modified VSVPWM are verified with various simulation results.