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An effective design to improve the efficiency of DPUs on FPGA
  • Lei, Yutian ;
  • Deng, Qingyong ;
  • Long, Saiqin ;
  • Liu, Shaohui ;
  • Oh, Sangyoon
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dc.contributor.authorLei, Yutian-
dc.contributor.authorDeng, Qingyong-
dc.contributor.authorLong, Saiqin-
dc.contributor.authorLiu, Shaohui-
dc.contributor.authorOh, Sangyoon-
dc.date.issued2020-12-01-
dc.identifier.issn1521-9097-
dc.identifier.urihttps://aurora.ajou.ac.kr/handle/2018.oak/36580-
dc.identifier.urihttps://www.scopus.com/inward/record.uri?partnerID=HzOxMe3b&scp=85102387372&origin=inward-
dc.description.abstractConvolutional neural networks (CNNs) have been widely used in various complicated problems, such as image classification, objection detection, semantic segmentation. To meet diversified CNN structures, the deep learning processing unit (DPU) is designed as a general accelerator on field programmable gate array (FPGA) to support various CNN layers, such as convolution, pooling, activation, etc. However, low DPU utilization and schedule efficiency appear when DPU used to multitask application completed by CNN models. In this paper, an effective design including multi-core with different size (MCDS) and DPU Plus is proposed to improve the efficiency of DPUs usage from the two dimensions of time and space. Through increasing the number of DPU cores on an FPGA and the utilization of single DPU core, the design of MCDS can effectively improve the overall throughput with restricted on-chip resources. Furthermore, the design of DPU Plus is proposed to improve the schedule efficiency of DPUs through simultaneously implementing DPU with other significant auxiliary modules of the application system on the same FPGA. Finally, a color space conversion module is implemented cooperate to the DPU cores to testify its performance, and the experimen shows that compared with running on the the CPU completely, it achieves16.2x acceleration, and increases the throughput of the entire system by 3.0x.-
dc.description.sponsorshipThis work is supported in part by the National Key Research and Development Program of China under Grant 2018YFB1003702, Natural Science Foundation of China under Grant No. 62032020, 62076214, Hunan Science and Technology Planning Project under Grant No.2019RS3019, and the Hunan Provincial Natural Science Foundation of China for Distinguished Young Scholars under Grant 2018JJ1025.-
dc.language.isoeng-
dc.publisherIEEE Computer Society-
dc.subject.meshApplication systems-
dc.subject.meshCNN models-
dc.subject.meshColor space conversion-
dc.subject.meshDifferent sizes-
dc.subject.meshEntire system-
dc.subject.meshProcessing units-
dc.subject.meshSemantic segmentation-
dc.subject.meshTwo-dimension-
dc.titleAn effective design to improve the efficiency of DPUs on FPGA-
dc.typeConference-
dc.citation.conferenceDate2020.12.2. ~ 2020.12.4.-
dc.citation.conferenceName26th IEEE International Conference on Parallel and Distributed Systems, ICPADS 2020-
dc.citation.editionProceedings - 2020 IEEE 26th International Conference on Parallel and Distributed Systems, ICPADS 2020-
dc.citation.endPage213-
dc.citation.startPage206-
dc.citation.titleProceedings of the International Conference on Parallel and Distributed Systems - ICPADS-
dc.citation.volume2020-December-
dc.identifier.bibliographicCitationProceedings of the International Conference on Parallel and Distributed Systems - ICPADS, Vol.2020-December, pp.206-213-
dc.identifier.doi10.1109/icpads51040.2020.00036-
dc.identifier.scopusid2-s2.0-85102387372-
dc.subject.keywordConvolutional neural network (CNN)-
dc.subject.keywordDeep learning processor unit (DPU)-
dc.subject.keywordEfficiency-
dc.subject.keywordField programmable gate array (FPGA)-
dc.type.otherConference Paper-
dc.description.isoafalse-
dc.subject.subareaHardware and Architecture-
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