A New Pipelined Output Data Reducer of BOST for Improved Parallelism

Abstract

To reduce the cost of memory production, built-off self-test (BOST) enables low-speed automatic test equipment to test the high-speed memory. To maximize the cost reduction benefit of BOST, it is crucial to test as many memories as possible using as few test output pins as possible. For this purpose, a new pipelined output data reducer called PODR is proposed for the output data reduction, and channel sharing between memories tested in parallel is introduced. The proposed structure is adopted to reduce hardware complexity while facilitating test output channel sharing between concurrently tested memories. Additionally, further output data reduction can be achieved by integrating the output data code into the pipelined structure. Output data reduction is also attainable by transmitting fault cell addresses using relative distance from the previously detected fault cells rather than the absolute addresses. Reducing the total code length can be achieved by the adoption of relative addressing, but this requires additional code transmission as its overhead. To mitigate this overhead, a revised approach to relative addressing is introduced. Consequently, as the number of memories tested in parallel increases, the amount of output data of PODR decreases and the number of normalized test output pins usages is reduced in half compared to the previous works.