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Comparative analysis of junctionless and inversion-mode nanosheet FETs for self-heating effect mitigation
  • An, Do Gyun ;
  • Kim, Garam ;
  • Kim, Hyunwoo ;
  • Kim, Sangwan ;
  • Kim, Jang Hyun
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dc.contributor.authorAn, Do Gyun-
dc.contributor.authorKim, Garam-
dc.contributor.authorKim, Hyunwoo-
dc.contributor.authorKim, Sangwan-
dc.contributor.authorKim, Jang Hyun-
dc.date.issued2024-01-01-
dc.identifier.issn1361-6641-
dc.identifier.urihttps://aurora.ajou.ac.kr/handle/2018.oak/33875-
dc.identifier.urihttps://www.scopus.com/inward/record.uri?partnerID=HzOxMe3b&scp=85181496622&origin=inward-
dc.description.abstractArtificial intelligence computing requires hardware like central processing units and graphic processing units for data processing. However, excessive heat generated during computations remains a challenge. The paper focuses on the heat issue in logic devices caused by transistor structures. To address the problem, the operational mechanism of the Junctionless Field-Effect Transistor (JLFET) is investigated. JLFET shows potential in mitigating heat-related issues and is compared to other nanosheet (ns) FETs. In the case of JL-nsFET, the change in mobility with increasing temperature is smaller compared to Con-nsFET, resulting in less susceptibility to lattice scattering and thermal resistance (Rth) in self-heating effect situation is 0.43 [K µW−1] for Con-nsFET and 0.414 [K µW−1] for JL-nsFET. The reason why the Rth of JL-nsFET is smaller than that of Con-nsFET is that JL-nsFET uses a source heat injection conduction mechanism and a large heat transfer area by using a bulk channel.-
dc.description.sponsorshipThis work was supported by the National Research Foundation of Korea (NRF) grant funded by the Korean government (MSIT) (No. 2022R1A2C1093201). The EDA tool was supported by the IC Design Education Center (IDEC), KOREA.-
dc.language.isoeng-
dc.publisherInstitute of Physics-
dc.subject.meshComparative analyzes-
dc.subject.meshField-effect transistor-
dc.subject.meshHighest temperature-
dc.subject.meshJunctionless-
dc.subject.meshNanosheet-FET-
dc.subject.meshSelf-heating effect-
dc.subject.meshThermal characteristics-
dc.subject.meshZero temperature coefficients-
dc.subject.meshZero-temperature coefficient-
dc.titleComparative analysis of junctionless and inversion-mode nanosheet FETs for self-heating effect mitigation-
dc.typeArticle-
dc.citation.number1-
dc.citation.titleSemiconductor Science and Technology-
dc.citation.volume39-
dc.identifier.bibliographicCitationSemiconductor Science and Technology, Vol.39 No.1-
dc.identifier.doi10.1088/1361-6641/ad10c4-
dc.identifier.scopusid2-s2.0-85181496622-
dc.identifier.urlhttp://iopscience.iop.org/0268-1242/-
dc.subject.keywordgate-all-around FET-
dc.subject.keywordhigh temperature-
dc.subject.keywordjunctionless-
dc.subject.keywordnanosheet-FET (nsFET)-
dc.subject.keywordself-heating effect (SHE)-
dc.subject.keywordthermal characteristics-
dc.subject.keywordzero-temperature coefficient (ZTC)-
dc.type.otherArticle-
dc.identifier.pissn0268-1242-
dc.description.isoafalse-
dc.subject.subareaElectronic, Optical and Magnetic Materials-
dc.subject.subareaCondensed Matter Physics-
dc.subject.subareaElectrical and Electronic Engineering-
dc.subject.subareaMaterials Chemistry-
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