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Optimization of Dual-workfunction Line Tunnel Field-effect Transistor with Island Source Junction
  • Yun, Chaewon ;
  • Kim, Sangwan ;
  • Cho, Seongjae ;
  • Cho, Il Hwan ;
  • Kim, Hyunwoo ;
  • Kim, Jang Hyun ;
  • Kim, Garam
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dc.contributor.authorYun, Chaewon-
dc.contributor.authorKim, Sangwan-
dc.contributor.authorCho, Seongjae-
dc.contributor.authorCho, Il Hwan-
dc.contributor.authorKim, Hyunwoo-
dc.contributor.authorKim, Jang Hyun-
dc.contributor.authorKim, Garam-
dc.date.issued2023-08-01-
dc.identifier.issn1598-1657-
dc.identifier.urihttps://aurora.ajou.ac.kr/handle/2018.oak/33647-
dc.identifier.urihttps://www.scopus.com/inward/record.uri?partnerID=HzOxMe3b&scp=85170355200&origin=inward-
dc.description.abstractIn this research, a novel dual workfunction (DWF) line tunnel field-effect transistor (LTFET) is optimized by using high WF gate-drain underlap and low WF gate-source underlap. Through numerical technology computer-aided design (TCAD) device simulations, it is confirmed that on-current (ION) can be increased by highly localized point tunneling while suppressing off-current (IOFF) by adjusting the distance between low-WF gate and source junction. Considering on-off current ratio (ION/IOFF) and the process variation, the distance between high-WF gate and source junction is optimized to be 3 to 5 nm.-
dc.description.sponsorshipThis research was supported by the National Research Foundation of Korea (NRF) funded by the Ministry of Science and ICT (MSIT) of Korea under Grants NRF-2020R1G1A1007430, NRF-2022R1A2C2092727 and NRF-2022M3I7A1078936. The EDA tool was supported by the IC Design Education Center (IDEC).-
dc.language.isoeng-
dc.publisherInstitute of Electronics Engineers of Korea-
dc.subject.meshDevice simulations-
dc.subject.meshDual workfunction-
dc.subject.meshJunction underlap-
dc.subject.meshLine tunneling field-effect transistor-
dc.subject.meshLow-power operation-
dc.subject.meshOptimisations-
dc.subject.meshSource junctions-
dc.subject.meshTechnology computer aided design-
dc.subject.meshTechnology computer-aided design device simulation-
dc.subject.meshTunneling field-effect transistors-
dc.titleOptimization of Dual-workfunction Line Tunnel Field-effect Transistor with Island Source Junction-
dc.typeArticle-
dc.citation.endPage214-
dc.citation.number4-
dc.citation.startPage207-
dc.citation.titleJournal of Semiconductor Technology and Science-
dc.citation.volume23-
dc.identifier.bibliographicCitationJournal of Semiconductor Technology and Science, Vol.23 No.4, pp.207-214-
dc.identifier.doi2-s2.0-85170355200-
dc.identifier.scopusid2-s2.0-85170355200-
dc.identifier.urlhttp://jsts.org/jsts/-
dc.subject.keywordDual workfunction-
dc.subject.keywordjunction underlap-
dc.subject.keywordline tunneling field-effect transistor (LTFET)-
dc.subject.keywordlow-power operation-
dc.subject.keywordTCAD device simulation-
dc.type.otherArticle-
dc.description.isoafalse-
dc.subject.subareaElectronic, Optical and Magnetic Materials-
dc.subject.subareaElectrical and Electronic Engineering-
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