Citation Export
| DC Field | Value | Language |
|---|---|---|
| dc.contributor.author | Yun, Chaewon | - |
| dc.contributor.author | Kim, Sangwan | - |
| dc.contributor.author | Cho, Seongjae | - |
| dc.contributor.author | Cho, Il Hwan | - |
| dc.contributor.author | Kim, Hyunwoo | - |
| dc.contributor.author | Kim, Jang Hyun | - |
| dc.contributor.author | Kim, Garam | - |
| dc.date.issued | 2023-08-01 | - |
| dc.identifier.issn | 1598-1657 | - |
| dc.identifier.uri | https://aurora.ajou.ac.kr/handle/2018.oak/33647 | - |
| dc.identifier.uri | https://www.scopus.com/inward/record.uri?partnerID=HzOxMe3b&scp=85170355200&origin=inward | - |
| dc.description.abstract | In this research, a novel dual workfunction (DWF) line tunnel field-effect transistor (LTFET) is optimized by using high WF gate-drain underlap and low WF gate-source underlap. Through numerical technology computer-aided design (TCAD) device simulations, it is confirmed that on-current (ION) can be increased by highly localized point tunneling while suppressing off-current (IOFF) by adjusting the distance between low-WF gate and source junction. Considering on-off current ratio (ION/IOFF) and the process variation, the distance between high-WF gate and source junction is optimized to be 3 to 5 nm. | - |
| dc.description.sponsorship | This research was supported by the National Research Foundation of Korea (NRF) funded by the Ministry of Science and ICT (MSIT) of Korea under Grants NRF-2020R1G1A1007430, NRF-2022R1A2C2092727 and NRF-2022M3I7A1078936. The EDA tool was supported by the IC Design Education Center (IDEC). | - |
| dc.language.iso | eng | - |
| dc.publisher | Institute of Electronics Engineers of Korea | - |
| dc.subject.mesh | Device simulations | - |
| dc.subject.mesh | Dual workfunction | - |
| dc.subject.mesh | Junction underlap | - |
| dc.subject.mesh | Line tunneling field-effect transistor | - |
| dc.subject.mesh | Low-power operation | - |
| dc.subject.mesh | Optimisations | - |
| dc.subject.mesh | Source junctions | - |
| dc.subject.mesh | Technology computer aided design | - |
| dc.subject.mesh | Technology computer-aided design device simulation | - |
| dc.subject.mesh | Tunneling field-effect transistors | - |
| dc.title | Optimization of Dual-workfunction Line Tunnel Field-effect Transistor with Island Source Junction | - |
| dc.type | Article | - |
| dc.citation.endPage | 214 | - |
| dc.citation.number | 4 | - |
| dc.citation.startPage | 207 | - |
| dc.citation.title | Journal of Semiconductor Technology and Science | - |
| dc.citation.volume | 23 | - |
| dc.identifier.bibliographicCitation | Journal of Semiconductor Technology and Science, Vol.23 No.4, pp.207-214 | - |
| dc.identifier.doi | 2-s2.0-85170355200 | - |
| dc.identifier.scopusid | 2-s2.0-85170355200 | - |
| dc.identifier.url | http://jsts.org/jsts/ | - |
| dc.subject.keyword | Dual workfunction | - |
| dc.subject.keyword | junction underlap | - |
| dc.subject.keyword | line tunneling field-effect transistor (LTFET) | - |
| dc.subject.keyword | low-power operation | - |
| dc.subject.keyword | TCAD device simulation | - |
| dc.type.other | Article | - |
| dc.description.isoa | false | - |
| dc.subject.subarea | Electronic, Optical and Magnetic Materials | - |
| dc.subject.subarea | Electrical and Electronic Engineering | - |
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