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고속 간소화 연속 제거 목록 극 부호 복호기의 저 복잡도 정렬 네트워크
| DC Field | Value | Language |
|---|---|---|
| dc.contributor.advisor | 선우명훈 | - |
| dc.contributor.author | 이용제 | - |
| dc.date.accessioned | 2025-01-25T01:36:04Z | - |
| dc.date.available | 2025-01-25T01:36:04Z | - |
| dc.date.issued | 2023-02 | - |
| dc.identifier.other | 32447 | - |
| dc.identifier.uri | https://dspace.ajou.ac.kr/handle/2018.oak/24575 | - |
| dc.description | 학위논문(석사)--아주대학교 일반대학원 :전자공학과,2023. 2 | - |
| dc.description.tableofcontents | I. Introduction 1 <br>II. Review of Polar Codes 4 <br>A. Polar Codes and Successive Cancelation Decoding 4 <br>B. Fast Simplified Successive Cancellation Decoding 5 <br>C. Successive Cancellation List Decoding 7 <br>D. Fast Simplified Successive Cancellation List Decoding 8 <br>III. Proposed Sorting Network 11 <br>A. Partitioned Sorting Network 11 <br>B. Candidate Path Exclusion for Sorter I 13 <br>C. Proposed Sorting Network 15 <br>D. Error Correction Performance Analysis 18 <br>E. Complexity Analysis 19 <br>IV. Implementation Results 23 <br>V. Conclusions 25 <br>Bibliography 25 | - |
| dc.language.iso | eng | - |
| dc.publisher | The Graduate School, Ajou University | - |
| dc.rights | 아주대학교 논문은 저작권에 의해 보호받습니다. | - |
| dc.title | 고속 간소화 연속 제거 목록 극 부호 복호기의 저 복잡도 정렬 네트워크 | - |
| dc.title.alternative | A Low-Complexity Sorting Network for a Fast Simplified SC List Polar Decoder | - |
| dc.type | Thesis | - |
| dc.contributor.affiliation | 아주대학교 대학원 | - |
| dc.contributor.department | 일반대학원 전자공학과 | - |
| dc.date.awarded | 2023-02 | - |
| dc.description.degree | Master | - |
| dc.identifier.localId | T000000032447 | - |
| dc.identifier.url | https://dcoll.ajou.ac.kr/dcollection/common/orgView/000000032447 | - |
| dc.subject.keyword | 오류정정부호 | - |
| dc.subject.keyword | 정보이론 | - |
| dc.subject.keyword | 회로설계 | - |
| dc.description.alternativeAbstract | Fast simplified successive cancellation list (FSSCL) decoding algorithms for polar codes have been proposed to achieve low latency and high error correction performance. However, the size of the metric sorters for FSSCL-single parity check (SPC) decoders significantly expands as the list size L increases. This paper proposes a partitioned sorting network (PSN) that reduces the complexity of metric sorter for FSSCL-SPC. The proposed PSN consists of two sorting networks. For the first sorting network, we analyze the order of the path metrics (PMs) and reduce the number of input candidate paths. Furthermore, for the second sorting network, the number of compare-and-swap units (CASUs) was reduced by identifying candidates that do not need comparison among the sorted candidates from the first sorting network. The FSSCL-SPC with the proposed PSN does not show any degradation in error correction performance compared to the existing FSSCL-SPC. The proposed PSN have up to 77% fewer CASUs and up to 102% higher operating frequencies than existing FSSCL-SPC sorting networks for L=8. | - |
- Appears in Collections:
- Graduate School of Ajou University > Department of Electronic Engineering > 3. Theses(Master)
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