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A Power Gating-based Energy-Efficient SCL Decoding Method for Polar Codes
| DC Field | Value | Language |
|---|---|---|
| dc.contributor.advisor | 선우명훈 | - |
| dc.contributor.author | HISHE HINTSA FISSEHA | - |
| dc.date.accessioned | 2025-01-25T01:35:51Z | - |
| dc.date.available | 2025-01-25T01:35:51Z | - |
| dc.date.issued | 2023-08 | - |
| dc.identifier.other | 33118 | - |
| dc.identifier.uri | https://dspace.ajou.ac.kr/handle/2018.oak/24284 | - |
| dc.description | 학위논문(석사)--아주대학교 일반대학원 :전자공학과,2023. 8 | - |
| dc.description.tableofcontents | I. Introduction 8 <br>II. Review of Polar Code 10 <br> A. Polar Codes and Successive Cancelation Decoding 10 <br> B. Successive Cancellation SC and List (SCL) Decoding 11 <br> C. Hardware Architecture of SCL Decoders 13 <br>III. Proposed Power Efficient SCL Decoding Method 16 <br> A. Power gated SCL 16 <br> B. Power Gating Scenario I 18 <br> C. Power Gating Scenario II 19 <br>IV. Results 21 <br> A. Error Correction Performance 21 <br> B. Computational Complexity 22 <br>V. Conclusions 24 <br>References 25 | - |
| dc.language.iso | eng | - |
| dc.publisher | The Graduate School, Ajou University | - |
| dc.rights | 아주대학교 논문은 저작권에 의해 보호받습니다. | - |
| dc.title | A Power Gating-based Energy-Efficient SCL Decoding Method for Polar Codes | - |
| dc.title.alternative | 파워게이팅 기반의 전력 효율적인 극 부호 SCL 복호 방법 | - |
| dc.type | Thesis | - |
| dc.contributor.affiliation | 아주대학교 대학원 | - |
| dc.contributor.department | 일반대학원 전자공학과 | - |
| dc.date.awarded | 2023-08 | - |
| dc.description.degree | Master | - |
| dc.identifier.localId | T000000033118 | - |
| dc.identifier.url | https://dcoll.ajou.ac.kr/dcollection/common/orgView/000000033118 | - |
| dc.subject.keyword | 5G | - |
| dc.subject.keyword | Decoding | - |
| dc.subject.keyword | Polar Codes | - |
| dc.subject.keyword | Power Gating | - |
| dc.subject.keyword | SCL | - |
| dc.subject.keyword | Successive Cancellation List | - |
| dc.description.alternativeAbstract | The successive cancellation list (SCL) decoding algorithm has been proposed to <br>enhance error correction in successive cancellation (SC) decoders for polar codes. <br>However, implementing SCL decoding in hardware requires multiple SC cores, <br>which leads to increased hardware complexity, power consumption, and <br>computational complexity. In this thesis, we propose a power-efficient SCL <br>decoding architecture that utilize power gating techniques to address these issues. <br>The proposed power gating-based SCL decoder architecture operates in the <br>following two scenarios. The first scenario involves shutting off a subset of the <br>decoding cores for the entire decoding process, using power gating. This approach <br>significantly reduces computational complexity by up to 75% in low noise <br>environments. The second scenario achieves low power consumption by <br>selectively shutting off some decoding cores during specific parts of the decoding <br>process. This method results in up to 19% of reduction in computational complexity. <br>The proposed architecture and scenarios are also evaluated in terms of error <br>correction performance, measured by the frame error rate (FER). The two scenarios <br>in which the proposed architecture operates provide us with a wider range of <br>performance options that span from a conventional SCL with a list size of L−M to <br>a conventional SCL with a list size of L. | - |
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- Graduate School of Ajou University > Department of Electronic Engineering > 3. Theses(Master)
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