A Cost-Effective Per-Pin ALPG for High-Speed Memory Testing - Lee, Juyong; Lee, Hayoung; Lee, Sooryeong; Kang, Sungho (IEEE Transactions on Very Large Scale Integration (VLSI) Systems, 2025)
An algorithmic pattern generator (ALPG) has been developed within automatic test equipment (ATE) due to the extensive number of test patterns required for testing the memories. Since shared-resource ALPG generates the test pattern using the same arithmetic instruction and timing across multiple input/output (I/O) pins, the maximum operating frequency is limited by the delay of the arithmetic operation. On the other hand, per-pin ALPG can achieve high-speed operations by generating one bit of the test pattern for each I/O pin. However, the hardware cost is significantly increased due to the need for individual instruction and pattern generator (PG) for each I/O pin. To address these limitations, a cost-effective per-pin ALPG for high-speed memory testing is proposed. The proposed per-pin ALPG can achieve high-speed operations, and the hardware resources for storing and decoding the instructions are shared among multiple I/O pins to reduce the hardware cost. The experimental results indicate that the proposed ALPG can achieve a higher speed than the conventional per-pin ALPG with a reasonable hardware cost comparable to the conventional shared-resource ALPG.
Keywords: Algorithmic pattern generator; Algorithmics; Automatic test equipment; Input-output; Pattern generator; Per-pin architecture; Shared resources; Shared-resource architecture; Test Pattern; Algorithmic pattern generator (ALPG); automatic test equipment (ATE); per-pin architecture; shared-resource architecture