Experimental Analysis on the Interaction Between Interface Trap Charges and Polarization on the Memory Window of Metal-Ferroelectric-Insulator-Si (MFIS) FeFET - Kim, Giuk; Choi, Hyojun; Lee, Sangho; Shin, Hunbeom; Lee, Sangmok; Nam, Yunseok; Kang, Hyunjun; Shin, Seokjoong; Kim, Hoon; Lim, Youngjin; Kim, Kang; Oh, Il Kwon; et al. (IEEE Transactions on Electron Devices, 2024)
In this study, we investigated the impact of unstable and stable interface trap charges (Qit) on PS switching in metal-ferroelectric-insulator-Si (MFIS) ferroelectric field-effect transistors (FeFETs), which vary with the thickness of the insulator. We also examine how these variations ultimately affect the various performance metrics of MFIS FeFETs. To achieve this, we varied the thickness of the insulator (tIL) in MFIS FeFETs to 1.5, 2.0, and 2.5 nm, thereby controlling the amount of Qit injected from the channel into the ferroelectric (FE)/insulator interface. As tIL decreases, the amount of Qit increases, which amplifies the electric field across the FE layer. As a result, PS switching enhances, and consequently, the MW characteristics of MFIS FeFETs improve. Furthermore, to analyze this in detail, we employed PS -Qit measurements on MFIS FeFETs to simultaneously extract unstable and stable Qit as well as PS and MW. The results show that as tIL increases to 1.5, 2.0, and 2.5 nm, Qit during program/erase (PGM/ERS) operations decreases to 100%, 61%, and 54%, respectively. This leads to a corresponding decrease in PS to 100%, 59%, and 52%. Additionally, after sufficient delay following the PGM/ERS operations, we observe that the proportion stable Qit compared to PS is 91%, regardless to tIL and the remaining 9% of PS contributes to the MW property. Consequently, as tIL increases to 1.5, 2.0, and 2.5 nm, the net charge decreases to 100%, 61%, and 54%, resulting in MW values of 1.85, 1.05, and 0.85 V, respectively. Finally, we analyzed the impact of Qit generation as a function of tIL on the variability and endurance characteristics of MFIS FeFETs.
Keywords: Erase operation; Experimental analysis; Ferroelectric field-effect transistor; Ferroelectric fieldeffect transistors (FeFET); Ferroelectric layers; Interface trap charge; Memory window; MW properties; Performance metrices; Program/erase; Ferroelectric field-effect transistor (FeFET); interface trap charges; memory window; polarization