선우명훈 신성경 2015-08 20159 https://aurora.ajou.ac.kr/handle/2018.oak/12965 학위논문(석사)--아주대학교 일반대학원 :전자공학과,2015. 8 Table of Contents Abstract List of Figures List of Tables I. Introduction 1 II. Existing FFT architecture 3 A. Memory based FFT architecture 3 B. Pipelined FFT architecture 3 C. MDC architecture for MIMO-OFDM systems 4 III. Proposed FFT architecture 6 A. Proposed Mixed-radix FFT algorithm 6 B. Proposed FFT architecture 8 i. Input RAM scheduling 10 ii. Stage 1 operations 13 iii. Commutators and delay elements at Stage 2 15 iv. Proposed complex constant multipliers at Stage 2 17 v. Stage 3, 4, and 5 Operations 23 IV. Performance Comparisons 27 V. Conclusion 30 Bibliography 31 kor The Graduate School, Ajou University 아주대학교 논문은 저작권에 의해 보호받습니다. 상수 복소 곱셈기를 적용한 고속 저면적 FFT 프로세서 High speed and Area-efficient FFT processor with Low Complexity Constant Complex Multipliers Thesis 아주대학교 일반대학원 일반대학원 전자공학과 2015. 8 Master http://dcoll.ajou.ac.kr:9080/dcollection/jsp/common/DcLoOrgPer.jsp?sItemId=000000020159 fast Fourier transform processor FFT processor Mixed-radix multi-path delay commutator MRMDC Orthogonal frequency division multiplexing OFDM This paper presents a high throughput and area efficient FFT processor for MIMO-OFDM systems based on the multi-path delay commutator (MDC) architecture. This paper proposes new scheduling schemes for reducing the number of complex multipliers and complex constant multipliers. In addition, this paper also proposes a novel structure of the complex constant multiplier which can be implemented without ROM and reduce the hardware complexity. The proposed MDC FFT processors can support 256, 128 and 64-point FFTs. The proposed processors have been designed and implemented with 90-nm CMOS technology. The proposed processors having eight-parallel data paths can achieve a high throughput rate up to 2.4 GS/s at 300 MHz.