Flash memory offers attractive features, such as non-volatile, shock resistance, fast access, and low power consumption. As flash memory receives much attention in data storage market, low priced multi-level-cell (MLC) flash memory has been widely adopted in the large-scale storage systems despite of its low performance. In order to hinder the low performance of MLC-flash memory, there has been a system design which optimizes chip-level-parallelism. This design enlarges the unit of page and block thus simultaneously executing operations on multiple chips.
Unfortunately previous algorithms of flash translation layer (FTL) generate many unused sectors within each page thus creating unnecessary write operations. As the concept of the chip-level-parallelism has been proposed recently, previous FTL algorithms show low compatibility to the chip-level-parallel flash memory. They execute unnecessary erase operations due to the low space utilization. As a solution, we propose “Hybrid Associative FTL (Hybrid-FTL)” for enhancing the performance of the chip-level-parallel flash memory system. The hybrid-FTL reduces the number of write operations by fully utilizing all the unused sectors. Furthermore, it reduces overall number of erase operations by using the state transition and reallocation blocks. It also prolongs the durability of the chip-level-parallel flash memory by modifying the merge operation.
We have compared hybrid-FTL to previous FTL algorithms by simulating them on 1 Tbytes of 4-chip-parallel flash memory. We have retrieved various traces from PCs using different file systems (NTFS and EXT3) and embedded devices. According to our experiment results, the hybrid-FTL significantly reduces the number of write operations by avoiding the sub-page-sets. Furthermore, it reduces the number of erase operations and evenly distributes them by “Hybrid Associative Sector Translation (HAST)”.
