Analysis of thermal effects according to channel and drain contact metal distance

Abstract

Unlike conventional planar metal-oxide-semiconductor field-effect transistors (MOSFET), multi-gate devices such as fin field-effect transistors (FinFET) suffer from serious electrical performance issues due to the self-heating effect (SHE) because the channel is surrounded by the gate dielectric. To address this issue, in this study, we analyzed the effect of the gap between the channel-drain junction and the drain metal on the SHE mitigation using 3D TCAD simulations of 14 nm node FinFET. The results show that reducing the gap reduces the maximum lattice temperature (Tmax) by 29.8 K, improves the maximum mobility (μmax) by 6.2 %, and improves the drain current (Ids) by 4.8 %. In addition, AC analysis results show that the power consumption is reduced by 6.7 % when the gap is minimized. In essence, it has been shown that the proposed structure could lead to comprehensive improvement in both electrical and thermal characteristics. However, reducing the gap increases the gate-drain capacitance (Cgd), which may negatively affect the signal propagation delay of complementary metal-oxide-semiconductor (CMOS). Therefore, this study derived the optimal gap between the channel and drain metals by balancing thermal improvement and performance degradation due to Cgd, thereby presenting a practical solution that can maintain device reliability while alleviating SHE.