Improvement of Thermal Characteristics and On-Current in Vertically Stacked Nanosheet FET by Parasitic Channel Height Engineering

Abstract

For improving thermal characteristics and on-current (I ON) in vertically stacked nanosheet field-effect transistor (NSFET), the effect of parasitic channel height (H parasitic) on thermal and electrical characteristics has been investigated. By increasing H parasitic, it has been demonstrated that the maximum lattice temperature (Tmax) could be improved from 428 K to 416 K, and thermal resistance (RTH) could be improved by 9.3 %. This thermal improvement has been achieved since the increased parasitic channel height could lead to the formation of effective heat sink. The relationship between H parasiticand the thermal characteristics of the device has rarely been addressed in previous studies, and we have explored this with a novel approach. In addition, regarding I ON, it has been demonstrated that the proposed device structure could have 19.7 % higher I ON, due to the increased fringing field effect. The origin and benefits of these thermal and electrical improvement have been thoroughly investigated through Synopsys Sentaurus three-dimensional (3D) technology computer-aided design (TCAD) simulation tool. The proposed NSFET structure is expected to be very strategic for the next-generation IC chip design with increased performance (from I ONimprovement) and enhanced reliability (from thermal improvement), at the same time.