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Simple Capacitor Voltage Balancing for Three-Level NPC Inverter Using Discontinuous PWM Method with Hysteresis Neutral-Point Error Band
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dc.contributor.authorAlsofyani, Ibrahim Mohd-
dc.contributor.authorLee, Kyo Beum-
dc.date.issued2021-11-01-
dc.identifier.urihttps://dspace.ajou.ac.kr/dev/handle/2018.oak/31977-
dc.description.abstractThree-level neutral-point-clamped (3L-NPC) voltage source inverters are widely used in many low- and medium-power applications. However, the 3L-NPC inverter has an inheritance issue of the neutral-point (NP) voltage unbalancing due to the deviation of dc-link capacitor voltages causing distortions for the output waveform quality. Generally, discontinuous pulsewidth modulation (DPWM) is used to diminish the stress on power transistors and prolong their lifespan, however; it is not capable of solving the issue of NP voltage unbalancing. Therefore, this article proposes a simple voltage balancing control based on DPWM with a hysteresis NP voltage band. The balancing control method is only activated once the capacitance voltage error exceeds the hysteresis band by generating a momentary offset on the opposite direction of the DPWM offset. In this way, both top and bottom capacitance voltages will converge within a predefined error band. Various hysteresis error bands are investigated by analyzing the power losses, total harmonic distortions, and common mode voltage. The advantages of this proposed method are its simplicity and ease of control while maintaining the features of DPWM. The effectiveness of the proposed method is validated using simulation and experimental results.-
dc.description.sponsorshipManuscript received December 18, 2020; revised March 5, 2021; accepted April 17, 2021. Date of publication April 22, 2021; date of current version July 30, 2021. This work was supported in part by the Korea Institute of Energy Technology Evaluation and Planning and in part by the Technology Innovation Program funded by the Ministry of Trade, Industry, and Energy (MOTIE, Korea) under Grants 20194030202370 and 20010854. Recommended for publication by Associate Editor D. Zhang. (Corresponding author: Kyo-Beum Lee.) Ibrahim Mohd Alsofyani is with the Department of Electrical and Computer Engineering, Ajou University, Suwon 16499, South Korea (e-mail: alsofyani2002@yahoo.com).-
dc.language.isoeng-
dc.publisherInstitute of Electrical and Electronics Engineers Inc.-
dc.subject.meshCapacitor voltage balancing-
dc.subject.meshDc-link capacitor voltages-
dc.subject.meshDiscontinuous pulse width modulations (DPWM)-
dc.subject.meshThree level NPC inverter-
dc.subject.meshThree-level neutral point clamped-
dc.subject.meshTotal harmonic distortion (THD)-
dc.subject.meshVoltage balancing control-
dc.subject.meshVoltage source inverter-
dc.titleSimple Capacitor Voltage Balancing for Three-Level NPC Inverter Using Discontinuous PWM Method with Hysteresis Neutral-Point Error Band-
dc.typeArticle-
dc.citation.endPage12503-
dc.citation.startPage12490-
dc.citation.titleIEEE Transactions on Power Electronics-
dc.citation.volume36-
dc.identifier.bibliographicCitationIEEE Transactions on Power Electronics, Vol.36, pp.12490-12503-
dc.identifier.doi10.1109/tpel.2021.3074957-
dc.identifier.scopusid2-s2.0-85104658905-
dc.identifier.urlhttps://ieeexplore.ieee.org/xpl/mostRecentIssue.jsp?punumber=63-
dc.subject.keywordDiscontinuous pulsewidth modulation (DPWM)-
dc.subject.keywordhysteresis neutral-point (NP) error band-
dc.subject.keywordNP voltage balancing-
dc.subject.keywordthree-level NP clamped inverter (3L-NPC)-
dc.description.isoafalse-
dc.subject.subareaElectrical and Electronic Engineering-
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