Citation Export
DC Field | Value | Language |
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dc.contributor.author | Park, Jong Hyeok | - |
dc.contributor.author | Park, Dong Joo | - |
dc.contributor.author | Chung, Tae Sun | - |
dc.contributor.author | Lee, Sang Won | - |
dc.date.issued | 2021-02-01 | - |
dc.identifier.issn | 2079-9292 | - |
dc.identifier.uri | https://dspace.ajou.ac.kr/dev/handle/2018.oak/31816 | - |
dc.description.abstract | An FTL (flash translation layer), which most flash storage devices are equipped with, needs to guarantee the consistency of modified metadata from a sudden power failure. This crash recovery scheme significantly affects the writing performance of a flash storage device during its normal operation, as well as its reliability and recovery performance; therefore, it is desirable to make the crash recovery scheme efficient. Despite the practical importance of a crash recovery scheme in an FTL, few works exist that deal with the crash recovery issue in FTL in a comprehensive manner. This study proposed a novel crash recovery scheme called FastCheck for a hybrid mapping FTL called Fully Associative Sector Translation (FAST). FastCheck can efficiently secure the newly generated address-mapping information using periodic checkpoints, and at the same time, leverages the characteristics of an FAST FTL, where the log blocks in a log area are used in a round-robin way. Thus, it provides two major advantages over the existing FTL recovery schemes: one is having a low logging overhead during normal operations in the FTL and the other to have a fast recovery time in an environment where the log provisioning rate is relatively high, e.g., over 20%, and the flash memory capacity is very large, e.g., 32 GB or 64 GB. | - |
dc.description.sponsorship | This work was supported by the Institute Information Communications Technology Planning Evaluation (IITP) (no. Conference 2015-0-00314); in part by the Support MSIT (Ministry for Programming of Science, ICT), Korea, under the High-Potential Individuals Global Training Program)(2020-0-01592), supervised by the IITP (Institute for Information & Communications Technology Planning & Evaluation); in part by the Basic Science Research Program through the National Research Foundation of Korea (NRF) funded by the Ministry of Education (2019R1F1A1058548). | - |
dc.language.iso | eng | - |
dc.publisher | MDPI AG | - |
dc.title | A crash recovery scheme for a hybrid mapping FTL in nand flash storage devices | - |
dc.type | Article | - |
dc.citation.endPage | 20 | - |
dc.citation.startPage | 1 | - |
dc.citation.title | Electronics (Switzerland) | - |
dc.citation.volume | 10 | - |
dc.identifier.bibliographicCitation | Electronics (Switzerland), Vol.10, pp.1-20 | - |
dc.identifier.doi | 10.3390/electronics10030327 | - |
dc.identifier.scopusid | 2-s2.0-85100196486 | - |
dc.identifier.url | https://www.mdpi.com/2079-9292/10/3/327 | - |
dc.subject.keyword | Address mapping | - |
dc.subject.keyword | Crash recovery | - |
dc.subject.keyword | Logging | - |
dc.subject.keyword | NAND flash memory | - |
dc.description.isoa | true | - |
dc.subject.subarea | Control and Systems Engineering | - |
dc.subject.subarea | Signal Processing | - |
dc.subject.subarea | Hardware and Architecture | - |
dc.subject.subarea | Computer Networks and Communications | - |
dc.subject.subarea | Electrical and Electronic Engineering | - |
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