This brief proposes a fully integrated output capacitor-less low-dropout regulator (LDO) using a voltage difference to time converter (VDTC). Proposed dynamic amplifier based VDTC allows low voltage operation and significantly reduces the quiescent current. The linear characteristics of VDTC result in output ripple-less operation and good regulation performance. Using direct output feedback through a small coupling capacitor, the gate voltage of the power transistor is instantly compensated to mitigate fluctuation of the output voltage when a sharp load transient occurs. Fabricated in 65 nm LP CMOS, the proposed LDO demonstrates a wide operation range with an input voltage range of 0.6-1.2 V and a load current of over 30 mA across all voltages without an output capacitor. With reduced output impedance due to direct output feedback, the measured undershoot is 158 mV, which is recovered in 9.6{μ }{s} , when the load current changes by 28 mA in 1 ns. The peak current efficiency is more than 99.99% and the figure of merit (FOM) is 0.202 fs. The active area of the control block is 0.002 mm2.
Manuscript received May 7, 2020; revised June 14, 2020; accepted June 29, 2020. Date of publication July 7, 2020; date of current version December 21, 2020. This work was supported by the National Research Foundation of Korea under Grant NRF-2019R1C1C1004927 and Grant NRF-2018R1C1B6003216, and in part by the Information Technology Research Center Support Program Supervised by the Institute for Information and Communications Technology Promotion under Grant IITP-2020-2018-0-01421. This brief was recommended by Associate Editor S. C. Wong. (Corresponding authors: Dongsuk Jeon; Dong-Woo Jee.) Kwanghyun Shin and Dongsuk Jeon are with the Graduate School of Convergence Science and Technology, Seoul National University, Seoul 08826, South Korea (e-mail: djeon1@snu.ac.kr).
