A multichannel field-programmable gate array (FPGA)-based time-to-digital converter (TDC) and its calibration techniques are presented. Herein, a frequency-tracker-based sliding-scale technique and a moving-average filter to improve the linearity and resolution are proposed. The error calibration technique automatically detects and corrects conversion errors caused by variations and mismatches in the propagation delays. The gain calibration extracts the average bin width of the fine TDC and resolves any linearity degradation in the coarse/fine interpolation architecture. The proposed techniques were applied to a four-channel TDC design implemented on a Xilinx Artix-7 FPGA. The measured differential and integral nonlinearities of all channels were within 0.51 least significant bit of 4.88 ps. The root-mean-squared resolution of the output code was 2.90-8.03 ps across a wide input range of 350 μ s.
This work was supported by National Research Foundation (NRF) of Korea under Grants RF-2018R1C1B6003216 and NRF-2019R1A5A1027055.Manuscript received March 10, 2020; accepted July 14, 2020. Date of publication July 23, 2020; date of current version November 24, 2020. This work was supported by National Research Foundation (NRF) of Korea under Grants RF-2018R1C1B6003216 and NRF-2019R1A5A1027055. The Associate Editor coordinating the review process was Dr. Eduardo Cabal-Yepez. (Corresponding author: Dong-Woo Jee.) The authors are with the Department of Electrical and Computer Engineering, Ajou University, Suwon 16944, South Korea (e-mail: dwjee@ajou.ac.kr). Digital Object Identifier 10.1109/TIM.2020.3011490
