In this paper, analysis and optimization of surrounding channel nanowire (SCNW) tunnel field-effect transistor (TFET) has been discussed with the help of technology computer-aided design (TCAD) simulation. The SCNW TFET features an ultra-thin tunnel layer at source sidewall and shows a high on-current (ION). In spite of the high electrical performance, the SCNW TFET suffers from hump effect which deteriorates subthreshold swing (S). In order to solve the issue, an origin of hump effect is analyzed firstly. Based on the simulation, the transfer curve in SCNW TFET is decoupled into vertical-and lateral-BTBTs. In addition, the lateral-BTBT causes the hump effect due to low turn-on voltage (VON) and low ION. Therefore, the device design parameter is optimized to suppress the hump effect by adjusting thickness of the ultra-thin tunnel layer. Finally, we compared the electrical properties of the planar, nanowire and SCNW TFET. As a result, the optimized SCNW TFET shows better electrical performance compared with other TFETs.
This research was supported in part by the Ajou University research fund, in part by the Brain Korea 185 21 Plus Project, in part by the MOTIE/KSRC under Grant 10080575 (Future Semiconductor Device Technology 186 Development Program), and in part by the NRF of Korea funded by the MSIT under Grant NRF-Grant NKF-2019M3b3AlA03U79739 and NKF-2019M3F3A1A02072091 (intelligent Semiconductor Technology Development Program). The EDA tool was supported by the IC Design Education Center (IDEC), Korea.
