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Current/Voltage Dual-Mode Single-Wire Simultaneous Bidirectional Interface Architecture for Sensor System
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Publication Year
2020-02-01
Publisher
Institute of Electrical and Electronics Engineers Inc.
Citation
IEEE Transactions on Biomedical Circuits and Systems, Vol.14, pp.12-19
Keyword
BidirectionalI/O interfacesensor applicationsimultaneoussingle-ended signalingtechnology scalablewearable interface
Mesh Keyword
BidirectionalSensor applicationssimultaneousSingle-endedWearable interfacesBiosensing TechniquesElectric WiringEquipment DesignLab-On-A-Chip DevicesWearable Electronic Devices
All Science Classification Codes (ASJC)
Biomedical EngineeringElectrical and Electronic Engineering
Abstract
This paper presents a simultaneous bidirectional asymmetrical serial interface architecture for sensor systems. The proposed current/voltage dual-mode signaling scheme provides system synchronous clock and continuous data transmission between sensor integrated circuit (IC) and system-on-a-chip (SoC) using a single wire, which minimizes pin requirements on packages. Two types of transceiver circuits were implemented in a 65 nm CMOS technology for the sensor IC and the SoC, and they were designed for transmission rates of 1 Mb/s and 250 Kb/s, core areas of 0.008 mm2 and 0.142 mm2, and power consumptions of 7.1 μW and 145.8 μW, respectively. The transceiver circuit for the sensor IC was also applied to a monolithic PPG sensor implemented in 180 nm CMOS, and the acquisition and transmission of PPG sensor data with the transceiver for the SoC, implemented in 65 nm, was successfully achieved.
Language
eng
URI
https://dspace.ajou.ac.kr/dev/handle/2018.oak/31150
DOI
https://doi.org/10.1109/tbcas.2019.2953240
Fulltext

Type
Article
Funding
Manuscript received August 7, 2019; revised October 5, 2019; accepted November 10, 2019. Date of publication November 13, 2019; date of current version February 4, 2020. This work was supported in part by the National Research Foundation of Korea under Grants NRF-2015R1C1A1A01051634 and NRF-2018R1C1B6003216. The chip fabrication and EDA tool were supported by IDEC, South Korea. This paper was recommended by Associate Editor S. Sonkusale. (Corresponding author: Dong-Woo Jee.) The authors are with the Department of Electrical and Computer Engineering, Ajou University, Suwon 16499, South Korea (e-mail: kjk4056@ajou.ac.kr; dwjee@ajou.ac.kr).
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Jee, Dong Woo지동우
Department of Electrical and Computer Engineering
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